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| 型號： | UC1682XHCZ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH-VOLTAGE MIXED-SIGNAL IC |
| 中文描述： | 高電壓混合信號集成電路 |
| 文件頁數(shù)： | 37/70頁 |
| 文件大小： | 1161K |
| 代理商： | UC1682XHCZ |
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UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
35
H
OST
I
NTERFACE
As summarized in the table below, UC1682
supports two parallel bus protocols, in either 8-bit
or 4-bit bus width, and three serial bus protocols.
Designers can either use parallel bus to achieve
high data transfer rate, or use serial bus to create
compact LCD modules.
Bus Type
Width
Access
BM[1:0]
D[7:6]
CS[1:0]
8080
6800
S8 (4wr)
S8uc (3wr)
Serial
Write Only
00
11
S9 (3wr)
8-bit
4-bit
Read/Write
00
0X
8-bit
4-bit
10
Data
11
Data
01
0X
Chip Select
00
10
01
1X
CD
WR0
Control/Data
_ _
R/W
EN
–
___ __
WR
___ __
RD
–
WR1
D[5:4]
D[3:0]
–
–
Data
Data
–
Data
Data
–
C
Data
Data
D0=SCK, D3=SDA
* Connect unused control pins and data bus pins to V
DD
or V
SS
CS
Disable
Interface
9
9
9
9
CS
Init bus
state
CD 1<=>0
Init bus
state
CD 1=>0
init color
mapping
9
9
9
9
RESET
Init bus
state
9
9
9
9
RESET
init color
mapping
9
9
9
9
8-bit
–
–
4-bit
–
9
–
9
S8 or S9
9
–
S8uc
CS disable bus interface – CS can be used to disable Bus Interface Write / Read Access.
CD refers to CD transitions within valid CS window. CD = 0 means write command or read status.
CS / CD Sync / RESET can be used to initialize bus state machine (like 4 bits / S8 / S9).
RESET can be pin reset / soft reset / power on reset.
CD can be used to initialize the multi-byte input RGB format to/from on-chip SRAM mapping.
Table 3:
Host interfaces Summary
P
ARALLEL
I
NTERFACE
The timing relationship between UC1682 internal
control signal RD, WR and their associated bus
actions are shown in the figure below.
The Display RAM read interface is implemented
as a two-stage pipe-line. This architecture
requires that, every time memory address is
modified, either in 8-bit mode or 4-bit mode, by
either
Set CA,
or
Set RA
command, a dummy
read cycle needs to be performed before the
actual data can propagate through the pipe-line
and be read from data port D[7:0].
There is no pipeline in write interface of Display
RAM. Data is transferred directly from bus buffer
to internal RAM on the rising edges of write
pulses.
8-
BIT
& 4-
BIT
B
US
O
PERATION
UC1682 supports both 8-bit and 4-bit bus width.
The bus width is determined by pin BM[1].
4-bit bus operation exactly doubles the clock
cycles of 8-bit bus operation, MSB followed by
LSB, including the dummy read, which also
requires two clock cycles. The bus cycle of 4-bit
mode is reset each time CD pin changes state
(when CS is active).
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