參數(shù)資料
型號： UC1682XHCZ
廠商： Electronic Theatre Controls, Inc.
英文描述： HIGH-VOLTAGE MIXED-SIGNAL IC
中文描述： 高電壓混合信號集成電路
文件頁數(shù)： 15/70頁
文件大?。?/td> 1161K
代理商： UC1682XHCZ
UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
13
C
OMMAND
T
ABLE
The following is a list of host commands supported by UC1682
C/D: 0: Control,
W/R: 0: Write Cycle,
# Useful Data bits
– Don’t Care
Command
C/D W/R D7
1 Write Data Byte
1
2 Read Data Byte
1
3 Get Status
0
Set Column Address LSB
0
4
Set Column Address MSB
0
5 Set Temp. Compensation
0
6 Set Panel Loading
0
7 Set Pump Control
0
0
8
(double byte command)
0
Set Scroll Line LSB
0
9
Set Scroll Line MSB
0
0
10 Set Row Address LSB
0
11 (double-byte command)
BIAS
Potentiometer
0
12 Set Partial Display Control
0
13 Set RAM Address Control
0
14 Set Fixed Lines
0
15 Set Line Rate
0
16 Set All-Pixel-ON
0
17 Set Inverse Display
0
18 Set Display Enable
0
19 Set Color Mask
0
20 Set LCD Mapping Control
0
21 Set Color Pattern
0
22 Set Color Mode
0
23 System Reset
0
24 NOP
0
0
25 (double byte command)
0
26 Set LCD Bias Ratio
0
27 Reset Cursor Update Mode
0
28 Set Cursor Update Mode
0
0
0
0
0
0
0
32 Starting Column Address
0
33 Starting Row Address
0
34 Ending Column Address
0
35 Ending Row Address
0
36 Enable window program
0
1: Data
1: Read Cycle
D6
#
#
MX
0
0
0
0
0
0
#
1
1
1
1
0
#
0
0
0
0
0
0
0
0
1
1
1
1
1
1
#
1
1
1
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
D5
#
#
MY
0
0
1
1
1
1
#
0
0
1
1
0
#
0
0
0
1
1
1
1
1
0
0
0
1
1
1
#
1
1
1
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
D4
#
#
WA
0
1
0
0
0
1
#
0
1
0
1
0
#
0
0
1
0
0
0
0
1
0
1
1
0
0
0
#
0
0
0
1
#
1
#
1
#
1
#
1
#
1
#
1
#
1
D3
#
#
DE
#
-
0
1
1
0
#
#
-
#
-
0
#
0
1
#
0
0
0
1
0
0
0
0
0
0
0
#
1
1
1
0
#
0
#
0
#
0
#
0
#
0
#
0
#
1
D2
#
#
WS OD
#
#
1
0
1
0
#
#
#
#
#
0
#
1
#
#
0
1
1
#
#
#
0
1
0
0
1
#
0
1
1
0
#
0
#
0
#
1
#
1
#
1
#
1
#
0
D1
#
#
D0
#
#
OS
#
#
#
#
#
R
#
#
#
#
#
1
#
#
#
#
#
#
#
#
#
#
#
#
0
1
Action
Write 1 byte
Read 1 byte
Get Status
Set CA[3:0]
Set CA[6:4]
Set TC[1:0]
Set PC[1:0]
Set PC[3:2]
Set APC[R][7:0],
R = 0, or 1
Set SL[3:0]
Set SL[6:4]
Set RA[3:0]
Set RA[6:4]
Default
N/A
N/A
N/A
0
0
0
1
11b
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
#
#
ID
0
0
0
0
0
0
#
0
0
0
0
1
#
1
1
1
1
1
1
1
1
1
1
1
1
1
1
#
1
1
1
1
-
1
-
1
-
1
#
1
#
1
#
1
#
1
#
#
#
#
#
0
#
#
#
#
#
0
#
#
#
#
#
0
1
#
#
#
0
#
1
1
Set Adv. Program Control
N/A
0
0
0
0
0
Set PM[7:0]
55H
Set LC[9:8]
Set AC[2:0]
Set FL[3:0]
Set LC[4:3]
Set DC[1]
Set DC[0]
Set DC[4:2]
Set MSK[2:0]
Set LC[2:0]
Set LC[5]
Set LC[7:6]
System Reset
No operation
For testing only.
Do not use.
Set BR[1:0]
AC[3]=0, CA=CR
AC[3]=1, CR=CA
0: Disable
001b
0
10b
0
0
110b
0
0
0 (BGR)
10b (56K)
N/A
N/A
TT
#
#
1
1
0
#
1
#
1
#
0
#
0
#
1
#
1
#
0
#
#
0
1
1
#
0
#
1
#
0
#
1
#
0
#
1
#
#
N/A
11b: 9
AC[3]=0
AC[3]=1
29 Set COM End
Set CEN[6:0]
79
30 Set Partial Display Start
Set DST[6:0]
0
31 Set Partial Display End
Set DEN[6:0]
79
0
Set WPC0[7:0]
0
0
Set WPP0[7:0]
0
0
Set WPC1[7:0]
103
0
Set WPP1[7:0]
79
Set AC[4]
0: Disable
* Other than commands listed above, all other bit patterns may result in undefined behavior.
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