參數(shù)資料
型號(hào): UC1682XHCZ
廠商: Electronic Theatre Controls, Inc.
英文描述: HIGH-VOLTAGE MIXED-SIGNAL IC
中文描述: 高電壓混合信號(hào)集成電路
文件頁(yè)數(shù): 24/70頁(yè)
文件大?。?/td> 1161K
代理商: UC1682XHCZ
U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999 ~
2003
22
ES Specifications
No-Dither Options:
DC[4]=0b disables dither function. Refer to
(18) Set Display Enable
for more information.
LC[7:6] = 00b (
RRR
-
GGG
-
BB
, 256 color )
One byte of input data is extended and stored to 12 RAM bits.
Data Write Sequence
1
st
Byte Write Data
D[7:0]
R2
R1
R0
G2
G1
G0
B1
B0
LC[7:6] = 01b (
RRRR
-
GGGGG
-
BBB
, 4K color )
12 bits of input data is stored to 12 RAM bits. 3 bytes of input data will be merged into 2 sets of RGB
data.
Data Write Sequence
1
st
Byte Write Data
2
nd
Byte Write Data
3
rd
Byte Write Data
D[7:0]
R3
G0
G4
R2
B2
G3
R1
B1
G2
R0
B0
G1
G4
R3
G0
G3
R2
B2
G2
R1
B1
G1
R0
B0
LC[7:6] =
10b
(
RRRRR
-
GGGGGG
-
BBBBB
, 56K color )
1-bit truncation for R/G, 2-bit for B. 16 bits input data truncated to 12 RAM bits.
Data Write Sequence
1
st
Byte Write Data
2
nd
Byte Write Data
D[7:0]
R4
G2
R3
G1
R2
G0
R1
B4
R0
B3
G5
B2
G4
B1
G3
B0
LC[7:6] = 11b (
RRRRRR
-
GGGGGGG
-
BBBBB
, 221K color )
2-bit truncation for per color. 18 out of 24 bits input data is truncated to 12 RAM bits.
Data Write Sequence
1
st
Byte Write Data
2
nd
Byte Write Data
3
rd
Byte Write Data
D[7:0]
R5
G6
R4
R4
G5
R3
R3
G4
R2
R2
G
3
R1
R1
G2
R0
R0
G1
--
--
G0
--
--
--
--
Data Read Sequence
for LC[7:6] = 0.
Data Read Sequence
1
st
Byte Read Data
2
nd
Byte Read Data
R/G/B: the input Red/Green/Blue data.
R/G
MN
: the Red/Green bits mapped from RGB input data.
for LC[7:6] = 1, 2, 3.
D[7:0]
R2
G
M1
R1
B2
R0
B1
R
M
B0
G2
0
G1
0
G0
0
G
M2
0
Data Read Sequence
1
st
Byte Read Data
2
nd
Byte Read Data
R/G/B
TN
: the N-th bit of after-truncated Red/Green/Blue input data
D[7:0]
R
T3
G
T0
R
T2
B
T2
R
T1
B
T1
R
T0
B
T0
G
T4
0
G
T3
0
G
T2
0
G
T1
0
(23) S
YSTEM
R
ESET
Action
System Reset
C/D W/R D7
0
0
D6
1
D5
1
D4
0
D3
0
D2
0
D1 D0
1
1
0
This command will activate the system reset. Control register values will be reset to their default values.
Data stored in RAM will not be affected.
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