參數(shù)資料
型號(hào)： UC1682XHCZ
廠商： Electronic Theatre Controls, Inc.
英文描述： HIGH-VOLTAGE MIXED-SIGNAL IC
中文描述： 高電壓混合信號(hào)集成電路
文件頁數(shù)： 23/70頁
文件大?。?/td> 1161K
代理商： UC1682XHCZ
UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
21
(22) S
ET
C
OLOR
M
ODE
Action
C/D W/R D7
0
0
D6
1
D5
0
D4
1
D3
0
D2
1
D1 D0
LC7 LC6
Set Color Mode LC [7:6]
Program color mode and RGB input pattern. Color mode (LC[7:6]) definition:
1
Dither Options:
DC[4]=1b enables dither function. Refer to
(18) Set Display Enable
for more information.
LC[7:6] = 00b (
RRR
-
GGG
-
BB
, 256 color )
One byte of input data is extended and stored to 12 RAM bits.
Data Write Sequence
1
st
Byte Write Data
D[7:0]
R2
R1
R0
G2
G1
G0
B1
B0
LC[7:6] = 01b (
RRRR
-
GGGG
-
BBBB
, 4K color )
1-bit extension for G, 1-bit dither for B. 12 bits of input data is stored to 12 RAM bits.
3 bytes of input data will be merged into 2 sets of RGB data.
Data Write Sequence
1
st
Byte Write Data
2
nd
Byte Write Data
3
rd
Byte Write Data
D[7:0]
R3
B3
G3
R2
B2
G2
R1
B1
G1
R0
B0
G0
G3
R3
B3
G2
R2
B2
G1
R1
B1
G0
R0
B0
LC[7:6] =
10b
(
RRRRR
-
GGGGGG
-
BBBBB
, 56K color )
1-bit dither for R/G, 2-bit dither for B. 16 bits input data dithered to 12 RAM bits.
Data Write Sequence
1
st
Byte Write Data
2
nd
Byte Write Data
D[7:0]
R4
G2
R3
G1
R2
G0
R1
B4
R0
B3
G5
B2
G4
B1
G3
B0
LC[7:6] = 11b (
RRRRRR
-
GGGGGGG
-
BBBBB
, 221K color )
2-bit dither per color. 18 out of 24 bits input data is dithered to 12 RAM bits.
Data Write Sequence
1
st
Byte Write Data
2
nd
Byte Write Data
3
rd
Byte Write Data
D[7:0]
R5
G6
B4
R4
G5
B3
R3
G4
B2
R2
G3
B1
R1
G2
B0
R0
G1
--
--
G0
--
--
--
--
Data Read Sequence
for LC[7:6] = 0.
Data Read Sequence
1
st
Byte Read Data
2
nd
Byte Read Data
R/G/B: the input Red/Green/Blue data.
R/G
MN
: the Red/Green bits mapped from RGB input data.
for LC[7:6] = 1, 2, 3.
D[7:0]
R2
G
M1
R1
B2
R0
B1
R
M
B0
G2
0
G1
0
G0
0
G
M2
0
Data Read Sequence
1
st
Byte Read Data
2
nd
Byte Read Data
R/G/B
DN
: the N-th bit of after-dither Red/Green/Blue input data
D[7:0]
R
D3
G
D0
R
D2
B
D2
R
D1
B
D1
R
D0
B
D0
G
D4
0
G
D3
0
G
D2
0
G
D1
0
Note
:
For system designers who want to use their own dithering algorithm, please set LC[7:6] = 10b (56k
color mode) and use the following input pattern to bypass on-chip dithering algorithm:
R3-R2-R1-R0
-1-
G4-G3-G2-G1-G0
-1-
B2-B1-B0
-1-0
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