參數(shù)資料
型號: UC1682XHCZ
廠商: Electronic Theatre Controls, Inc.
英文描述: HIGH-VOLTAGE MIXED-SIGNAL IC
中文描述: 高電壓混合信號集成電路
文件頁數(shù): 17/70頁
文件大?。?/td> 1161K
代理商: UC1682XHCZ
UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
15
C
OMMAND
D
ESCRIPTION
(1) W
RITE
D
ATA
T
O
D
ISPLAY
M
EMORY
Action
Write data
C/D W/R D7
1
0
D6
D5
D4
D3
D2
D1 D0
8bits data write to SRAM
UC1682 will convert input RAM data to 12-bits of RGB data. Please refer to command
(22)
Set Color Mode
for detail data write sequence. The format of 12 bits RGB data is as following:
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
G
B
(2) R
EAD
D
ATA
F
ROM
D
ISPLAY
M
EMORY
Action
Read data
C/D W/R D7
1
1
D6
D5
D4
D3
D2
D1 D0
8bits data from SRAM
Each RGB triplet is stored as 12-bit in the display RAM. Each 12 bits RGB data takes 2 RAM read cycles.
The data read will start with the high byte D[11:4] and then low byte {D[3:0],4’b0000}. The read out RGB
data is
after-dither
for 56K color and 221K color mode and
after-extension
for 256 color mode.
R3
R2
R1
R0
G4
G3
G2
G1
G0
B2
B1
B0
0
0
0
0
1st Read
2nd Read
Write/Read Data Byte (command 1/2) operation uses internal Row Address register (RA) and Column
Address register (CA). RA and CA can be programmed by issuing
Set Row Address
and
Set Column
Address
commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the CA
boundary, and system programmers need to set the values of RA and CA explicitly. If WA is ON (1), when
CA reaches end of column address, CA will be reset to 0 and RA will be increased or decreased, depending
on the setting of Row Increment Direction (RID, AC[2]). When RA reaches the boundary of RAM (i.e. RA = 0
or 79), RA will be wrapped around to the other end of RAM and continue.
(3) G
ET
S
TATUS
Action
Get Status
C/D W/R D7
0
1
D6
MX MY WA DE WS OD OS
D5
D4
D3
D2
D1 D0
ID
Status flag definitions:
ID
: Provide access to ID pin connection status.
MX
: Status of register LC[1], mirror X.
MY
: Status of register LC[2], mirror Y.
WA:
Status of register AC[0]. Automatic column/row wrap around.
DE
: Display enable flag. DE=1 when display is enabled
WS
: OTP Command Succeeded
OD
: OTP Option (Yes/No)
OS
: OTP action status
(4) S
ET
C
OLUMN
A
DDRESS
Action
C/D W/R D7
0
0
0
0
D6
0
0
D5
0
0
D4
0
1
D3
CA3 CA2 CA1 CA0
-
CA6 CA5 CA4
D2
D1 D0
Set Column Address LSB CA[3:0]
Set Column Address MSB CA[6:4]
Set SRAM column address for read/write access. CA is counted in RGB triplets, not individual SEG
electrode.
0
0
CA value range:
0~103
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