參數(shù)資料
型號(hào)： TVP5041PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 99/106頁(yè)
文件大?。?/td> 501K
代理商： TVP5041PFP
2–76
2.13.66 Interrupt Configuration Register A
VIP address
1C2h
PHI address
C2h
I2C address
C2h
7
6
5
4
3
2
1
0
Reserved
YUV output enable A
Interrupt A
Interrupt polarity A
YUV output enable A
0 = YUV pins are 3-state
1 = YUV pins are active if other conditions are met
Interrupt A
0 = Interrupt terminal is not active
1 = Interrupt terminal is active
Reflects state of interrupt A on the external pin
Interrupt polarity
0 = Interrupt is active low
1 = Interrupt is active high
The interrupt configuration register A is used to configure the polarity of the external in interrupt pin. Note that when
the interrupt is configured for active low the terminal is driven low when active and 3-state when inactive
(open-collector). Conversely, when the terminal is configured for active high it is driven high for active and driven low
for inactive. The interrupt A bit is read-only.
2.13.67 VIP Teletext FIFO
VIP address
1400h
PHI address
N/A
I2C address
N/A
7
6
5
4
3
2
1
0
Teletext Data FIFO [7:0]
The teletext FIFO can be accessed via the regular teletext FIFO register at address B0 if PHI or I2C host interface
is enabled, or via VIP FIFO A at location 4 in VIP FIFO address space if VIP host interface is enabled.
Reading this location returns 1 byte from the FIFO that stores teletext transactions. If the FIFO is empty, a read returns
the same value as the previous read. It is the driver software’s or application software’s responsibility to assure that
the correct number of bytes per transaction are read out from the teletext FIFO. The transaction length depends on
the whether the data is NABTS, WST-NTSC, or WST-PAL.
2.13.68 VIP Program RAM Write
VIP address
1500h
PHI address
N/A
I2C address
N/A
7
6
5
4
3
2
1
0
Program RAM Write Data
If the PHI or I2C host interface is enabled, the program RAM can be written via the nonVIP program RAM write register
at address 7E. If the VIP host interface is enabled, the program RAM can be written via VIP FIFO B at location 5 in
the VIP FIFO address space.
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