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參數(shù)資料
| 型號： | TVP5041PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 57/106頁 |
| 文件大?。?/td> | 501K |
| 代理商： | TVP5041PFP |
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2–38
VBI FIFO
The VBI FIFO containing sliced VBI data can be read directly by the PHI host.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read VBI FIFO
1
0
Data from FIFO
Status/Interrupt Register
The status/interrupt register provides the host with information regarding the source of an interrupt. After an interrupt
condition is set it can be reset by writing a 1 to the appropriate bit in the status/interrupt register. Section 2.14 contains
a description of the PHI status/interrupt register.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Access status/interrupt register
1
Data from status/interrupt register
2.8.11 Parallel Host Interface Microcode Write Operation
A microcode write operation is required to down load microcode to the TVP5041 program RAM after power-up reset.
During the write cycle, the internal microprocessors program counter resets and points to location zero in the program
RAM and remains reset. Upon completion of the write operation, a microprocessor CLEAR-RESET operation is
required. This is performed by writing into the 7F register to clear reset and resume the microprocessor function.
(There is no specific data requirement to be written into the 7F register, any data will resume the microprocessor
function.)
To avoid violating PHI cycle time requirements during a microcode write operation the host can poll the cycle complete
bit in the PHI status register after writing each byte data to the PHI data register. Alternatively, the cycle complete
enable bit in the interrupt enable register (indirect address C1) can be set to generate an interrupt for the host when
a write has been completed.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode register address
0
1
0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode register data
0
1
First byte of microcode data
(Wait for cycle complete status or interrupt.)
Write microcode register data
0
1
Second byte of microcode data
(Wait for cycle complete status or interrupt.)
Write microcode register data
0
1
Last byte of microcode data
(Wait for cycle complete status or interrupt.)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear-reset register address
0
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear-reset dummy data
0
1
Dummy data
(Wait for cycle complete status or interrupt.)
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