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參數(shù)資料
| 型號： | TVP5041PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 58/106頁 |
| 文件大?。?/td> | 501K |
| 代理商： | TVP5041PFP |
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2–39
2.8.12 Parallel Host Interface Microcode Read Operation
The data read from indirect register 8E is read from the TVP5041 program RAM. During the read cycle, the internal
microprocessors program counter resets and points to location zero in the program RAM and remains reset. Upon
completion of the read operation, a microprocessor CLEAR-RESET operation is required. This is performed by
writing into the 7F register to clear reset and resume the microprocessor function. (There is no specific data
requirement to be written into the 7F register, any data will resume the microprocessor function.)
To avoid violating PHI cycle time requirements during a microcode read operation the host can poll the cycle complete
bit in the PHI status register after writing to the PHI address register. Alternatively, the cycle complete enable bit in
the interrupt enable register (indirect address C1) can be set to generate an interrupt for the host when the read data
is available in the PHI data register.
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write program RAM read address
0
1
0
1
0
(Wait for cycle complete status or interrupt)
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read program RAM read data
0
1
data
NOTE: Repeat Steps 1 and 2 until all program RAM data has been read.
Step 3
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear-reset register address
0
1
Step 4
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear-reset register data
0
1
Dummy data
(Wait for cycle complete status or interrupt)
2.9
VBI Data Processor
The TVP5041 VBI data processor slices, parses, and performs error checking on teletext data contained in the
vertical blanking interval or during active lines. Teletext formats supported are North American Basic Teletext
Specification (NABTS) equivalent to ITU-R BT.653 system C, and World System Teletext (WST) equivalent to ITU-R
BT.653 system B. Data is stored in an internal FIFO and may be read via the host port or transmitted as ancillary data
in the digital video stream in BT.656 mode. The VBI data FIFO holds up to 14 lines of NABTS or 11 lines of WST data.
Interrupts generated by the VBI data processor are configurable to enable host synchronization for retrieval of
full-field teletext data.
Closed caption data may also be sliced by the VBI data processor and is stored in a register accessible via the host
port.
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