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參數(shù)資料
| 型號： | TVP3025-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 74/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-175 |
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2–60
Table 2–28. Status Register (RS value = 11010)
BIT
NAME
VALUES
DESCRIPTION
SR07
Reserved (logic 0)
SR06
0: Idle
BT485 register translation state machine indicator. If this bit is a logic 1, then
the TVP3020 index registers should not be accessed.
1: Busy
SR05,
SR04
Revision bit values
These two bits are for revision numbers Initially they contain zeros
These two bits are for revision numbers. Initially they contain zeros.
SR03
SENSE bit
SENSE bit. If it is a logic 0, one or more of the IOR, IOG, and IOB outputs have
exceeded the internal voltage reference. See Section 2.4.14.
SR02
0: Write cycle
Read/write cycle status. This bit provides read/write status when the register
select bits 0, 3, 4, or 7 (hex) have been written.
1: Read cycle
SR01,
SR00
00: Red color component
These bits reflect the color component address of the next read/write cycle
when the palette, cursor color, or overscan registers are accessed.
01: Green color component
10: Blue color component
2.4.16.3 Accessing Command Registers 3 and 4
A fourth and fifth command register, command register 3 and command register 4 are added to address the
extended functions of the TVP3025 and remain backward compatible with the BT485. Since there are only
4 register select lines defined on the BT485 (all 16 combinations are used), command register 3 and
command register 4 must be accessed indirectly. Command registers 3 and 4 are accessed with the
following sequence of operations:
1.
2.
3.
4.
5.
6.
Set RS3 – RS0 to 0110, command register 0.
Write a logic 1 to CR07.
Set RS3 – RS0 to 0000, address register.
Write address register to 0000 0001 (command register 3) or 0000 0010 (command register 4).
Set RS3 – RS0 to 1010.
Read or write command register 3 or 4.
With this indirect addressing, the status register can be accessed by writing 0000 0000 to the address
register, as in step 4 above.
To address the 64
×
64 cursor RAM, CR31 and CR30 must be written to provide the 2 MSBs for the 10-bit
address counter. Therefore, to set the counter to access a particular location in the RAM array, these 2 bits
must be written to command register 3 before the lower 8 bits are written to the address counter through
the MPU port. As the 10-bit address counter auto-increments, the new value of this counter can be read back
through CR31 and CR30. The contents of this register are reset with the assertion of the external RESET
terminal. See Section 2.4.15.5 and the notes in that section.
2.4.16.4 Cursor-Position (x,y) Registers
These registers are used to specify the (x,y) coordinates of the 64
×
64
×
2 hardware cursor. The cursor
registers contain low and high value registers. The last value written by the MPU to these registers is the
value returned on a read. These registers can be read/written by the MPU at any time. Bits D4–D7 of both
high registers are ignored.
CURSOR-POSITION X HIGH
D6
D5
D4
CURSOR-POSITION X LOW
D6
D5
D4
Data Bit
D7
D3
D2
D1
D0
D7
D3
D2
D1
D0
X Position
0
0
0
0
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
RS value = 11101
RS value = 11100
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| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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