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參數資料
| 型號： | TVP3025-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調色器） |
| 文件頁數： | 36/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-175 |
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2–22
2.3.8.6
Multiplex-Control Registers
The pixel port multiplexer is controlled by two 8-bit registers in the indirect register map (see Table 2–3). The
various multiplexing modes can be selected according to the following table.
Table 2–8. Multiplex Mode and Bus-Width Selection
MODE
SUB-
MODE
MULTIPLEX-
CONTROL
REGISTER 1
(HEX)
MULTIPLEX-
CONTROL
REGISTER 2
(HEX)
DATA
BITS
PER
PIXEL
(see
Note 8)
PIXEL
BUS
WIDTH
MULTI-
PLEX
RATIO
(see
Note 9)
OVERLAY
BITS
PER
PIXEL
TABLE
REFERENCE
(see
Note 10)
VGA
80
98
8
8
1
NA
v1
Pseud
Color
d
1
80
00
1
4
4
NA
s1
80
01
1
8
8
NA
s2
80
02
1
16
16
NA
s3
80
03
1
32
32
NA
s4
80
04
1
64
64
NA
s5
2
80
08
2
4
2
NA
s6
80
09
2
8
4
NA
s7
80
0A
2
16
8
NA
s8
80
0B
2
32
16
NA
s9
80
0C
2
64
32
NA
s10
3
80
10
4
4
1
NA
s11
80
11
4
8
2
NA
s12
80
12
4
16
4
NA
s13
80
13
4
32
8
NA
s14
80
14
4
64
16
NA
s15
4
80
19
8
8
1
NA
s16
80
1A
8
16
2
NA
s17
80
1B
8
32
4
NA
s18
80
1C
8
64
8
NA
s19
NOTES:
8. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,
often referred to as the number of bit planes.
9. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists
of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK.
Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK
divide ratio is not automatically set by mode selection but must be programmed in the output-clock-
selection register by the user.
10. This column is a reference to Tables 2–9 through 2–11, where the actual manipulation of pixel information
and pixel latching sequences are illustrated for each of the multiplexing modes.
11. It is recommended that all unused input terminals be connected to ground to conserve power.
12. Auxiliary control register bit 0 and color-key-control register bit 4 default to palette graphics at reset. If direct
color operation is desired, then these bits must be set to logic 0.
13. Multiplex-control register 1 bit 3 must be set to logic 1 for direct or true-color mode operation. This bit setting
is different than the TVP3020 VIP.
14. If the device is reset to the BT485 mode, to program the multiplexer for the TVP3020 true-color modes,
true-color control register bit 2 must be set to a logic 0. This is automatically the case if the device is reset
into the TVP3020 mode.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-135AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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