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參數(shù)資料
| 型號： | TVP3025-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 14/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-175 |
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1–8
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
104
VGABL
I
(TTL
capability)
VGA blank input. VGABL is active (low).
VGAHS,
VGAVS
102, 103
I
(TTL
capability)
VGA horizontal and vertical sync inputs. These signals are used to
generate the sync level on the green current output. They can be either
polarity, and the TVP3025 passes the polarities to HSYNCOUT and
VSYNCOUT without change.
VGA0–VGA7
88–95
I
(TTL
capability)
VGA pass-through bus. This bus can be selected as the pixel bus for
VGA mode, but it does not allow for any multiplexing.
VSYNCOUT
68
O
(TTL
capability)
Vertical sync output after pipeline delay. For system mode, the output
polarity can be programmed but for VGA mode, the output carries the
same polarity as the input.
WR
43
I
(TTL
capability)
Write strobe input. A logic 0 on this terminal initiates a write to the
register map. As with RD, write transfers are asynchronous and
initiated on the low-going edge of WR (see Figure 3–1).
XTAL1,
XTAL2
119, 120
I
(TTL
capability)
Series resonant crystal oscillator. This may be used as the reference
for the on-chip frequency synthesis PLLs and can be selected through
the input-clock-selection register.
8/6
98
I
(TTL
capability)
DAC resolution selection. This terminal is used to select the data bus
width (8 or 6 bits) for the DAC when in the TVP3020 mode and is
essentially provided in order to maintain compatibility with the
IMSG176. When this terminal is a logical 1 and the 8/6 terminal is
enabled (miscellaneous-control register bit 2 is logic 0), 8-bit bus
transfers are used with D7 the MSB and D0 the LSB. For 6-bit bus
operation (8/6 terminal is a logical 0), while the color palette still has
the 8-bit information D5 shifts to the bit 7 position with D0 shifted to the
bit 2 position and the two LSBs are filled with zeros at the output
multiplexer to the DAC. The palette holding register zeroes the two
MSBs when it is read in the 6-bit mode. If miscellaneous-control
register bit 2 is logic 1, then the 8/6 terminal is disabled and 8/6
operation is specified by bit 3 of the miscellaneous-control register.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| TVP3409-135 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-135AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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