參數(shù)資料
型號(hào)： TTSI2K32T
英文描述： 2048-Channel, 32-Highway Time-Slot Interchanger
中文描述： 2048通道，32道時(shí)隙交換器
文件頁(yè)數(shù)： 64/66頁(yè)
文件大小： 1321K
代理商： TTSI2K32T
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
64
Lucent Technologies Inc.
Ordering Information
DS99-045T1E1 Replaces DS97-475TIC to Incorporate the Following Updates
1. Page 8, Pin D17, added overline to show active-low (TRST).
2. Page 8, removed duplicate E1, E2, E3, E4, E14, E15, E16, and E17 pins.
3. Page 20, Highway Data Rate Selection section, added paragraph on meeting the 8.192 Mbits/s bandwidth
requirement for a transmit highway pair at the bottom of the page.
4. Page 22, updated Figure 10, Virtual and Physical Frames on page 22.
5. Page 24, Reset Sequence section, added paragraph on BIST requirement.
6. Page 25—page 28, Low-Latency and Frame-Integrity Modes section updated.
7. Page 29, Test-Pattern Generation section updated.
8. Page 29 and page 30, Test-Pattern Checking section updated.
9. Page 38, Table 15, General Command Register (0x00), removed last sentence in description of bit 2 and bit 1.
10. Page 38, Table 15, General Command Register (0x00), updated bit 0 symbol from GXEN to GXE.
11. Page 39, Table 16, Software Reset Register (0x01), updated bit 0, software reset description.
12. Page 41, Table 22, Interrupt Status Register (0x07), updated bit 4 and bit 2 to reserved status.
13. Page 42, Table 23, Interrupt Mask Register (0x08), updated bit 4 and bit 2 to reserved status.
14. Page 42, Table 23, Interrupt Mask Register (0x08), bit 3 symbol changed from MASKED to MASKERD.
15. Page 44, Table 25, Test-Pattern Style Register (0x0A), updated test-pattern descriptions.
16. Page 45, Table 27, Test-Pattern Checker Upper Time-Slot Register (0x0C), updated description.
17. Page 45, Table 28, Test-Pattern Checker Lower Time-Slot Register (0x0D), updated description.
18. Page 45, Table 30, Test-Pattern Error Injection Register (0x0F), changed register name from test-pattern error
selection register to test-pattern error injection register and added sentence to end of description.
19. Page 47, Table 35, Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i), updated bit 3—bit 2 sym-
bol from XCEOFF to XFBOFF.
20. Page 48, Table 37, Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i), updated bit 2 symbol name
from XEN to XE.
21. Page 49, Table 38, Receive Highway Configuration Register (Byte 0) (0x1800 + 4i), updated bit 3—bit 2 symbol
from RCEOFF to RFBOFF.
22. Page 51, Transmit Highway 3-State Options section and Table 41, Transmit Highway 3-State Options updated.
23. Page 52, Data Store Memory section updated.
24. Page 53, Table 44, Connection Store Memory (Byte 0), changed TSA symbol to RTSA and updated
description.
25. Page 53, Table 45, Connection Store Memory (Byte 1), changed PORTNUM symbol to RXHWY.
26. Page 52—page 54, Connection Store Memory section updated.
27. Page 55, Absolute Maximum Ratings table, power dissipation, P
D
, updated from 450 mW to 440 mW.
28. Page 56, Table 46, Clock Specifications, updated clock period stability for CK.
29. Page 61, Timing Characteristics section, updated Figure 22, TDM Highway Timing and text.
30. Page 61, Table 50, TDM Highway Timing, timing parameter t26, minimum changed from 15 ns to 10 ns.
Device Code
Package
Temperature
Comcode
(Ordering Number)
108269770
TTSI2K32T3BAL
217-pin PBGA
–40
°
C to +85
°
C
相關(guān)PDF資料
PDF描述
TTSI2K32T3BAL 2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時(shí)隙交換機(jī))
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TTSI4K32T3BAL 4096-Channel, 32-Highway Time-Slot Interchanger
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