參數(shù)資料
型號(hào)： TTSI2K32T
英文描述： 2048-Channel, 32-Highway Time-Slot Interchanger
中文描述： 2048通道，32道時(shí)隙交換器
文件頁數(shù)： 34/66頁
文件大?。?/td> 1321K
代理商： TTSI2K32T
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
34
Lucent Technologies Inc.
JTAG Boundary-Scan Specification
(continued)
Instruction Register
The instruction register (IR) is 4 bits in length. Table 13 shows the BS instructions implemented by the TTSI2K32T.
Table 13. TTSI2K32T’s Boundary-Scan Instructions
The instructions not supported in TTSI2K32T are INTEST, RUNBIST, and TOGGLE. A fixed binary 0001 pattern
(the 1 into the least significant bit) is loaded into the IR in the CAPTURE IR controller state. The IDCODE instruc-
tion (binary 0001) is loaded into the IR during the test-logic-reset controller state and at powerup.
The following is an explanation of the instructions supported by TTSI2K32T and their effect on the devices' pins.
EXTEST:
This instruction enables the path cells, the pins of the ICs, and the connections between ASICs to be tested via the
circuit board. The test data can be loaded in the chosen position of the BS register by means of the SAMPLE/PRE-
LOAD instruction. The EXTEST instruction selects the BS register as the test data register. The data at the function
inputs is clocked into the BS register on the rising edge of TCK in the CAPTURE DR state. The contents of the BS
register can be clocked out via TDO in the SHIFT DR state. The value of the function outputs is solely determined
by the contents of the data clocked into the BS register and only changes in the UPDATE DR state on the falling
edge of TCK.
IDCODE:
Information regarding the manufacturer’s ID for Lucent, the IC number, and the version number can be read out
serially by means of the IDCODE instruction. The IDCODE register is selected, and the BS register is set to normal
mode in the UPDATE IR state. The IDCODE is loaded at the rising edge of TCK in the CAPTURE DR state. The
IDCODE register is read out via TDO in the SHIFT DR state.
HIGHZ:
All 3-statable outputs are forced to a high-impedance state, and all bidirectional ports are forced to an input state
by means of the HIGHZ instruction. The impedance of the outputs is set to high in the UPDATE IR state. The func-
tion outputs are only determined in accordance with another instruction if a different instruction becomes active in
the UPDATE IR state. The BYPASS register is selected as the test data register. The HIGHZ instruction is imple-
mented in a similar manner to that used for the BYPASS instruction.
SAMPLE/PRELOAD:
The SAMPLE/PRELOAD instruction enables all the input and output pins to be sampled during operation (SAM-
PLE) and the result to be output via the shift chain. This instruction does not impair the internal logic functions.
Defined values can be serially loaded in the BS cells via TDI while the data is being output (PRELOAD).
Instruction
Code
Act. Register
TDI
→
TDO
Boundary Scan
Mode
Function
Output Defined Via
EXTEST
0000
TEST
Test external
connections
Read Manuf.
Register
3-state
Sample/load
Min shift path
—
BS Register
IDCODE
0001
Identification
NORMAL
Core Logic
HIGHZ
0100
0101
1111
—
BYPASS
Boundary Scan
BYPASS
BYPASS
X
Output—High Impedance
Core Logic
Core Logic
Output—High Impedance
SAMPLE/PRELOAD
BYPASS
EVERYTHING ELSE
NORMAL
NORMAL
X
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