參數(shù)資料
型號： TTSI2K32T
英文描述： 2048-Channel, 32-Highway Time-Slot Interchanger
中文描述： 2048通道，32道時隙交換器
文件頁數(shù)： 4/66頁
文件大?。?/td> 1321K
代理商： TTSI2K32T
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
4
Lucent Technologies Inc.
List of Tables
Tables
Page
Table 1. Data Rate and Switch Size Examples....................................................................................................... 5
Table 2. Pin Assignments for a 217-Pin PBGA—Pin Number Order ...................................................................... 8
Table 3. Pin Assignments for a 217-Pin PBGA—Signal Name Order................................................................... 10
Table 4. TTSI2K32T Pin Descriptions................................................................................................................... 12
Table 5. The TSI Family........................................................................................................................................ 17
Table 6. Rx Highway Data Rate Options............................................................................................................... 20
Table 7. Tx Highway Data Rate Options............................................................................................................... 20
Table 8. Time-Slot Separation Required for Transmission with Minimum Latency (0 Offsets)............................. 25
Table 9. Offset Difference and Its Effect on Frame for Transmission.................................................................... 27
Table 10. Offset Difference Boundaries ................................................................................................................ 27
Table 11. TAP Controller States in the Data Register Branch............................................................................... 33
Table 12. TAP Controller States in the Instruction Register Branch...................................................................... 33
Table 13. TTSI2K32T’s Boundary-Scan Instructions ............................................................................................ 34
Table 14. TTSI2K32T Register Summary ............................................................................................................. 36
Table 15. General Command Register (0x00) ...................................................................................................... 38
Table 16. Software Reset Register (0x01) ............................................................................................................ 39
Table 17. BIST Command Register (0x02) ........................................................................................................... 39
Table 18. Idle Code 1 Register (0x03)................................................................................................................... 40
Table 19. Idle Code 2 Register (0x04)................................................................................................................... 40
Table 20. Idle Code 3 Register (0x05)................................................................................................................... 40
Table 21. Global Interrupt Mask Register (0x06)................................................................................................... 40
Table 22. Interrupt Status Register (0x07) ............................................................................................................ 41
Table 23. Interrupt Mask Register (0x08).............................................................................................................. 42
Table 24. Test Command Register (0x09) ............................................................................................................ 43
Table 25. Test-Pattern Style Register (0x0A)........................................................................................................ 44
Table 26. Test-Pattern Checker Highway Register (0x0B).................................................................................... 45
Table 27. Test-Pattern Checker Upper Time-Slot Register (0x0C)....................................................................... 45
Table 28. Test-Pattern Checker Lower Time-Slot Register (0x0D)....................................................................... 45
Table 29. Test-Pattern Checker Data Register (0x0E).......................................................................................... 45
Table 30. Test-Pattern Error Injection Register (0x0F).......................................................................................... 45
Table 31. Test-Pattern Error Counter (Byte 0) (0x10)........................................................................................... 46
Table 32. Test-Pattern Error Counter (Byte 1) (0x11)........................................................................................... 46
Table 33. Test-Pattern Generator Data Register (0x12) ....................................................................................... 46
Table 34. Version Register (0x13)......................................................................................................................... 46
Table 35. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i) ......................................................... 47
Table 36. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i) ......................................................... 48
Table 37. Transmit Highway Configuration Register (Byte 2) (0x1002 + 4i) ......................................................... 48
Table 38. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i) .......................................................... 49
Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i) .......................................................... 50
Table 40. Receive Highway Configuration Register (Byte 2) (0x1802 + 4i) .......................................................... 50
Table 41. Transmit Highway 3-State Options........................................................................................................ 51
Table 42. Address Scheme for Data Store Memory ............................................................................................. 52
Table 43. Address Scheme for Connection Store Memory .................................................................................. 52
Table 44. Connection Store Memory (Byte 0)....................................................................................................... 53
Table 45. Connection Store Memory (Byte 1)....................................................................................................... 53
Table 46. Clock Specifications .............................................................................................................................. 56
Table 47. Asynchronous Read and Write Interface Timing Using DT Handshake................................................ 57
Table 48. Asynchronous Microprocessor Interface Timing Using Only CS .......................................................... 58
Table 49. Synchronous Microprocessor Interface Timing..................................................................................... 60
Table 50. TDM Highway Timing............................................................................................................................ 61
Table 51. JTAG Interface Timing........................................................................................................................... 62
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