參數(shù)資料
型號： TTSI2K32T
英文描述： 2048-Channel, 32-Highway Time-Slot Interchanger
中文描述： 2048通道，32道時隙交換器
文件頁數(shù)： 14/66頁
文件大?。?/td> 1321K
代理商： TTSI2K32T
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
14
Lucent Technologies Inc.
Pin Information
(continued)
Table 4. TTSI2K32T Pin Descriptions
(continued)
*I
u
indicates internal 100 k
pull-up resistor, and I
d
indicates internal 17.5 k
pull-down resistor.
Symbol
TXOE[0—31]
Type
*
O
Description
Transmit Output Enables 0—31.
These output pins reflect the active/high-imped-
ance status for the corresponding transmit highways. They are continuously driven
to reflect the status of the output enables of the transmit highways, regardless of
whether or not external driver mode is enabled via the ED (bit 6) in the general com-
mand register. The external driver for transmit highway [i] should be enabled when
TXOE[i] is a 1.
Also see Table 41, Transmit Highway 3-State Options, on page 51 for other meth-
ods of 3-stating the transmit highways.
JTAG Test Data Input.
TDI
I
u
I
I
u
I
d
TCK
TMS
JTAG Test Clock.
Maximum 10 MHz.
JTAG Test Mode Select.
TRST
JTAG Test Reset (Active-Low).
To disable the JTAG interface, tie TRST low or
leave unconnected.
Test Data Output.
3.3 V Supply.
All V
DD
leads must be connected to the 3.3 V supply.
Ground.
3.3 V PLL Supply.
V
SS
PLL and V
DD
PLL should be decoupled with a high-speed
capacitor with a value in the range of 2
μ
F—5
μ
F.
PLL Ground.
V
SS
PLL and V
DD
PLL should be decoupled with a high-speed capaci-
tor with a value in the range of 2
μ
F—5
μ
F.
No Connect.
This pin must be left unconnected.
TDO
V
DD
V
SS
V
DD
PLL
O
P
P
P
V
SS
PLL
P
NC
—
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