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參數資料
| 型號： | TSW5071N |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION |
| 中文描述： | 可編程解碼器/濾鏡組合第二代 |
| 文件頁數： | 7/32頁 |
| 文件大?。?/td> | 284K |
| 代理商： | TSW5071N |
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POWER-DOWN STATE
Following a period of activity in the powered-up
state the power-down state may be re-entered by
writing any of the control instructions into the serial
control port with the ”P” bit set to ”1” It is recom-
mendedthat thechipbe powereddownbeforewrit-
ing any additional instructions. In the power-down
state, all non-essential circuitry is de-activated and
theD
X
0 andD
X
1outputsarein thehighimpedance
TRI-STATEcondition.
Thecoefficientsstoredin theHybridBalancecircuit
and theGain Controlregisters,the datain the LDR
and ILR, and all control bits remain unchanged in
the power-down state unless changed by writing
new datavia the serialcontrol port,which remains
operational. The outputs of the Interface Latches
also remain active, maintainingthe ability to moni-
tor and control a SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF
X
I, is a high imped-
ance summinginputwhichis usedas thedifferenc-
ingpointfortheinternalhybridbalancecancellation
signal. No external componentsare neededto set
the gain. Following this circuit is a programmable
gain/attenuationamplifierwhichiscontrolledbythe
contents of the Transmit Gain Register (see Pro-
grammable Functions section). An active prefilter
then precedesthe 3rd order high-passand 5th or-
der low-pass switched capacitor filters. The A/D
converterhas acompressingcharacteristicaccord-
ing to the standardCCITT A or
μ
255 coding laws,
whichmustbe selectedbya controlinstructiondur-
ing initialization(seetable1 and2).A precisionon-
chipvoltagereferenceensuresaccurateand highly
stable transmissionlevels. Any offset voltage aris-
ing in the gain-set amplifier, the filters or the com-
paratoris cancelledbyan internalauto-zerocircuit.
Each encode cycle begins immediately following
the assigned Transmit time-slot. The total signal
delay referencedto the startof the time-slot is ap-
proximately 165
μ
s (due to the Transmit Filter)
plus 125
μ
s (due to encoding delay), which totals
290
μ
s. Data is shifted out on D
X
0 or D
X
1 during
the selected time slot on eight rising edges of
BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive
PCM RegisterviatheD
R
0orD
R
1pinduringthe se-
lectedtime-slotonthe8fallingedgesof BCLK.The
Decoder consistsof an expandingDAC with either
A or
μ
255law decodingcharacteristic, whichis se-
lectedbythesamecontrolinstructionusedtoselect
the Encode law during initialization. Following the
Decoderisa 5thorderlow-passswitchedcapacitor
filter with integral Sin x/x correction for the 8 kHz
sample and hold. A programmablegain amplifier,
which must be set by writing to the Receive Gain
Register,isincluded,andfinallyaPost-Filter/Power
Amplifier capable of driving a 300
load to
±
3.5
V, a 600
load to
±
3.8 Vor 15 k
loadto
±
4.0 V
at peak overload.
A decode cycle begins immediately after each re-
ceive time-slot, and 10
μ
s later the Decoder DAC
output is updated. The total signal delay is 10
μ
s
plus 120
μ
s (filter delay) plus 62.5
μ
s (1/2 frame)
whichgives approximately190
μ
s.
PCM INTERFACE
The FS
X
and FS
R
frame syncinputsdeterminethe
beginning of the 8-bit transmit and receive time-
slots respectively. They may have any duration
from a single cycle of BCLK to one MCLK period
LOW. Two different relationships may be estab-
lishedbetweentheframesyncinputsandtheactual
time-slotson thePCM bussesbysettingbit 3 inthe
Control Register (see table 2). Non delayed data
mode is similar to long-frame timing on the
ETC5050/60 series of devices : time-slots being
nominallycoincident with the risingedge of the ap-
propriate FS input. The alternative is to use De-
layed Data mode which is similar to short-frame
sync timing, in which each FS input must be high
at least a half-cycleof BCLK earlier than the time-
slot.
TheTime-SlotAssignmentcircuit onthedevicecan
onlybeusedwithDelayedDatatiming.Whenusing
Time-Slot Assignment, the beginning of the first
time-slot in a frameis identifiedby the appropriate
FSinput.Theactualtransmitandreceivetime-slots
are then determined by the internalTime-Slot As-
signment counters. Transmit and Receive frames
and time-slots may be skewed from each other by
any number of BCLK cycles.
During each assigned transmit time-slot, the se-
lected D
X
0/1 output shifts data out from the PCM
register on the rising edges of BCLK. TS
X
0 (or
TS
X
1 as appropriate)also pulls low for the first 7
1/2 bit times of the time-slot to control the TRI-
STATE Enable of a backplane line driver. Serial
PCM data is shifted into the selected D
R
0/1 input
during each assigned Receive time slot on the
falling edges of BCLK. D
X
0 or D
X
1 and D
R
0 or
D
R
1 are selectableon the TS5070 only.
SERIALCONTROL PORT
Control information and data are written into or
readback from COMBO IIG via the serial control
portconsistingof thecontrolclockCCLK; theserial
data input/output CI/O (or separate input CI, and
output CO on the TS5070only); and the ChipSe-
lect input CS. All control instructions require 2
bytes,as listedintable1, withtheexceptionof asin-
gle bytepower-up/downcommand. The byte1 bits
are used as follows: bit 7 specifies power-up or
power-down;bits 6, 5, 4 and 3 specifythe register
address; bit 2 specifies whetherthe instructions is
read or write; bit 1 specifies a one or two byte in-
TS5070 - TS5071
7/32
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