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參數(shù)資料
| 型號： | TSW5071N |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION |
| 中文描述： | 可編程解碼器/濾鏡組合第二代 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 284K |
| 代理商： | TSW5071N |
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Alternatively, the internal time-slot assignment
counters and comparators can be used to access
anytime-slotinaframe,usingtheframesyncinputs
as markerpulses for the beginningof transmit and
receivetime-slot0. In this mode, a framemaycon-
sist ofup to64 time-slotsof 8bitseach.A time-slot
is assignedbya2-byteinstructionasshownintable
1 and6. The last6 bits of the secondbyte indicate
the selected time-slot from 0-63 using straight bi-
nary notation. A new assignment becomes active
on the second frame following the end of the Chip
Select forthe secondcontrol byte.The ”EN”bit al-
lows thePCMinputsD
R
0/1 oroutputsD
X
0/1 asap-
propriate,to be enabled or disabled.
Time-Slot Assignmentmode requires that the FS
X
and FS
R
pulsesmustconformto thedelayedtiming
formatshown in figure6.
PORT SELECTION
On the TS5070 only, an additional capability is
available : 2 Transmit serial PCM ports, D
X
0 and
D
X
1, and2 receiveserialPCM ports,D
R
0 andD
R
1,
are providedto enabletwo-way space switching to
be implemented. Port selections for transmit and
receive are made within the appropriatetime-slot
assignmentinstructionusingthe”PS”bitin thesec-
ond byte.
On the TS5071,only ports D
X
0 and D
R
0 areavail-
able,therefore the ”PS” bit MUSTalways be setto
0 for thesedevices.
Table 6 shows the format for the second byte of
bothtransmitand receivetime-slotandportassign-
ment instructions.
TRANSMIT GAIN INSTRUCTION BYTE2
The transmit gain can be programmed in 0.1 dB
steps by writing to the Transmit Gain Register as
defined in tables 1 and 7. This corresponds to a
range of 0 dBm0 levels at VF
X
I between 1.619
Vrms and 0.087 Vrms (equivalent to + 6.4 dBm to
– 19.0 dBm in 600
).
To calculate the binary code for byte 2 of this in-
struction for any desired input 0 dBm0 level in
Vrms, take the nearest integer to the decimal
number given by :
and convert to the binary equivalent.Some exam-
ples are given in table 7.
Bit Number
0dBm0 Test Leve at VF
X
I
In dBm (Into 600
)
7
6
5
4
3
2
1
0
In Vrms (approx.)
0
0
0
0
0
0
0
0
No Output
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
– 19
– 18.9
0.087
0.088
1
0
1
1
1
1
1
1
0
0.775
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
+6.3
+6.4
1.60
1.62
Table 7:
Byte2 of Transmit Gain Instructions.
(*) State at power initialization
RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB
stepsbywritingtotheReceiveGainRegisterasde-
finedin table1 and8. Notethe followingrestriction
on outputdrive capability :
a) 0 dBm0 levels
≤
8.1dBm at VF
R
O may be
driven into a load of
≥
15 k
to GND,
b) 0 dBm0 levels
≤
7.6dBm at VF
R
O may be
driven into a load of
≥
600
to GND,
c) 0 dBm levels
≤
6.9dBmat VF
R
O may be driven
into a load of
≥
300
to GND.
To calculate the binary code for byte 2 of this in-
struction for any desired output 0 dBm0 level in
Vrms,takethe nearestintegerto the decimalnum-
ber given by :
200 X log
10
(V/
√
6
) + 174
a
n
d convert to the binary equivalent. Some exam-
ples are given in table 8.
200 X log
10
(V/
√
6
) + 191
TS5070 - TS5071
11/32
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