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參數(shù)資料
| 型號(hào)： | TSS463C |
| 廠商： | Atmel Corp. |
| 英文描述： | VAN Data Link Controller with Serial Interface |
| 中文描述： | 凡數(shù)據(jù)與串行接口鏈路控制器 |
| 文件頁數(shù)： | 6/59頁 |
| 文件大?。?/td> | 492K |
| 代理商： | TSS463C |
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6
TSS463C
7601B–AUTO–02/06
Figure 3.
SPI Data Stream
SCLK: Serial Clock
The master device provides the serial clock for the slave devices. Data is transferred
synchronously with this clock in both directions. The master and the slave devices
send/receive a data byte during an eight-clock pulse sequence.
MOSI: Master Out Slave In
The MOSI pin is the master device data output (CPU) and the slave device data input
(TSS463C). Data is transferred serially from the master to the slave on this line; most
significant bit (MSB) first, least significant bit (LSB) last.
MISO: Master In Slave Out
The MISO pin is configured as the slave device data output (TSS463C) and as master
device data input (CPU). When the slave device is not selected (SS = 1), this pin is in
high impedance state.
SS: Slave Select
The SS pin is the slave chip select. It is low active. A low state on the Slave Select input
allows the TSS463C to accept data on the MOSI pin and send data on the MISO pin.
The Slave Select signal must not toggle between each transmitted byte and should be
left at a low level during the whole SPI frame. SS must be asserted to inactive high level
at the end of the SPI frame.
As mentioned before, if SS is not asserted, MISO pin is in a high impedance state and
incoming data is not driven to the serial data register.
SPI Protocol
The general format of the data communication in the SPI frame between the TSS463C
and the host is a bit-for-bit exchange on each SCLK clock pulse. Data is arranged in the
TSS463C such that the significance of a bit is determined by its position from the start
for output and from the end for input, most significant bit (MSB) is sent first. Bit
exchanges in multiples of 8 bits are allowed.
The Idle Clock Polarity (CPOL) and the Clock Phase (CPHA) are not programmable: the
CPOL and CPHA values to be programmed in the master (CPU) are CPOL = CPHA = 1.
This is available for all modes. Waveforms with transmit and sample points are shown in
Figure 6.
0x55
SCLK
MOSI
SS
SPI 8 Pulses
0x66
MISO
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSS463C-TERA-9 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC ASICS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TSS463C-TERZ-9 | 制造商:Atmel Corporation 功能描述: |
| TSS463C-TESZ-9 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC ASICS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TSS463D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| TSS463R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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