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參數(shù)資料
| 型號： | TSS463C |
| 廠商： | Atmel Corp. |
| 英文描述： | VAN Data Link Controller with Serial Interface |
| 中文描述： | 凡數(shù)據(jù)與串行接口鏈路控制器 |
| 文件頁數(shù)： | 14/59頁 |
| 文件大?。?/td> | 492K |
| 代理商： | TSS463C |
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14
TSS463C
7601B–AUTO–02/06
VAN Protocol
Line Interface
There are three line inputs and one line output available on the TSS463C. that of the
three inputs to use is either programmable by software or automatically selected by a
diagnosis system.
The diagnosis system continuously monitors the data received through the three inputs,
and compares it with each other and the selected bitrate. It then chooses the most reli-
able input according to the results.
The data on the line is encoded according to the VAN standard ISO/11519-3. This
means that the TSS463C is using a two level signal having a recessive (1) and a domi-
nant (0) state. Furthermore, due to the simple medium used, all data transmitted on the
bus is also received simultaneously.
The VAN protocol is hence a CSMA/CD (Carrier Sense Multiple Access Collision Detec-
tion) protocol, allowing for continuous bitwise arbitration of the bus, and non-destructive
(for the higher priority messa ge) collision detection.
Figure 10.
CSMA/CD Arbritration
In addition to the VAN specification there is also a pulsed coding of the dominant and
recessive states. This mode is intended to be used with an optical or radio link. In this
mode the dominant state for the transmitter is a low pulse (2x prescaled clocks at the
beginning of the bit) and the recessive state is just a high level. When receiving in this
mode it is not the state of the signal itself that is decoded, but the edges. Also, reception
is imposed on the RxD0 input, and the diagnosis system does not operate correctly.
In addition, in this mode there is an internal loopback in the circuit since optical trans-
ceivers are not able to receive the signal that they transmit.
Node a: TxD
Node a loses the arbitration
Node a releases the bus
Node b wins the arbitration
Node c loses the arbitration
Node c releases the bus
R
D
Node b: TxD
R
D
Node c: TxD
R
D
On Bus: DATA
R
D
Arbitration field
R: Recessive Level
D: Dominant Level
1
2
3
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSS463C-TERA-9 | 功能描述:網(wǎng)絡控制器與處理器 IC ASICS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TSS463C-TERZ-9 | 制造商:Atmel Corporation 功能描述: |
| TSS463C-TESZ-9 | 功能描述:網(wǎng)絡控制器與處理器 IC ASICS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| TSS463D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| TSS463R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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