參數(shù)資料
型號: TSS461F
廠商: Atmel Corp.
英文描述: VAN Data Link Controller
中文描述: 凡數(shù)據(jù)鏈路控制器
文件頁數(shù): 7/57頁
文件大?。?/td> 397K
代理商: TSS461F
7
7615A–AUTO–02/06
TSS461F
Figure 3.
Intel Read and Write Cycles
Motorola Mode
In Motorola mode, the WR pin becomes the R/W command, the RD pin must be connected to
ground and the CS pin becomes the E strobe. There is no separate chip select input. For exam-
ple, if some external decoder is used, this decoder should not drive the E input high unless the
processors E output is high as well.
See Figure 4 for the Motorola read and write cycles. The main difference between Intel and
Motorola mode is that the timing in Intel mode is referenced to the command signals (RD and
WR), but in Motorola mode the reference is the E signal.
Figure 4.
Motorola Read and Write Cycles
Interrupts
If an event occurs in the TSS461F, that needs the attention of the processor, this will be sig-
nalled on the active low, open-drain interrupt request pin. The events that create this request is
controlled by the internal registers.
Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B),
the INT pin will be released momentarily. This enables the TSS461F to work with processors
that have either edge or level sensitive interrupt inputs.
ALE
AD[7:0]
RD
WR
CS
ADDRESS
DA
TA
TO
BE
WRITTEN
ADDRESS
DA
T
A
READ
WRITE CYCLE
READ CYCLE
ALE
AD[7:0]
VSS (RD)
R/W (WR)
E (CS)
ADDRESS
DATA TO BE
WRITTEN
ADDRESS
DATA
READ
WRITE CYCLE
READ CYCLE
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