參數(shù)資料
型號(hào)： TSS461C-TDRZ
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： VAN Data Link Controller
中文描述： 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO24
封裝： ROHS COMPLIANT, SO-24
文件頁(yè)數(shù)： 9/57頁(yè)
文件大?。?/td> 423K
代理商： TSS461C-TDRZ
9
TSS461C
4193G–AUTO–12/04
Oscillator
An oscillator is integrated in the TSS461C, and consists of an inverting amplifier which
the input is XTAL1 and the output XTAL2.
A parallel resonance quartz crystal or ceramic resonator must be connected to these
pins. As shown in Figure 1, two capacitors have to be connected from the crystal pins to
ground. The values of C1 depend on the frequency chosen and can be selected using
the graphic given in Figure 33.
If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1
input.
Note, that this pin will behave as a CMOS level compatible Schmitt trigger input. In this
case, the XTAL2 output should be left unconnected. The oscillator also features a buff-
ered clock output pin CKOUT. The signal on this pin is directly buffered from the XTAL1
input, without inversion.
There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground,
and unless this pin is firmly connected to ground, with decoupling capacitors, the oscilla-
tor will not operate correctly.
The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for fac-
tory use, and the functionality of this mode is not specified in any way.
Furthermore, it is subject to change without notice, the only exception is for incoming
inspection tests using the test program.
The clock signal is then fed to the clock generator generate all the necessary timing sig-
nals for the operation of the circuit. The clock generator is controlled by a 4-bit code
called the clock divider.
F
TSCLK
F
1
n
16
------------------
=
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