參數(shù)資料
型號(hào)： TSPC860XRMZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁數(shù)： 24/93頁
文件大?。?/td> 1601K
代理商： TSPC860XRMZQU66D
24
TSPC860 [Preliminary]
2129B–HIREL–12/04
PD[7]
RTS3
T15
Bidirectional
General-Purpose I/O Port D Bit 7—Bit 7 of the general-purpose I/O
port D.
RTS3—Active low request to send output indicates that SCC3 is
ready to transmit data.
PD[6]
RTS4
V16
Bidirectional
General-Purpose I/O Port D Bit 6—Bit 6 of the general-purpose I/O
port D.
RTS4—Active low request to send output indicates that SCC4 is
ready to transmit data.
PD[5]
REJECT2
U15
Bidirectional
General-Purpose I/O Port D Bit 5—Bit 5 of the general-purpose I/O
port D.
REJECT2—This input to SCC2 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not match.
PD[4]
REJECT3
U16
Bidirectional
General-Purpose I/O Port D Bit 4—Bit 4 of the general-purpose I/O
port D.
REJECT3—This input to SCC3 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not match.
PD[3]
REJECT4
W16
Bidirectional
General-Purpose I/O Port D Bit 3—Bit 3 of the general-purpose I/O
port D.
REJECT4—This input to SCC4 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not match.
TCK
DSCK
Hi-Z (Pulled
up on rev 0 to
rev A.3)
H16
Input
Provides clock to scan chain logic or for the development port logic.
Should be tied to Vcc if JTAG or development port are not used.
TMS
Pulled up
G18
Input
Controls the scan chain test mode operations. Should be tied to
power through a pull-up resistor if unused.
TDI
DSDI
Pulled up (Hi-
Z on rev 0 to
rev A.3)
H17
Input
Input serial data for either the scan chain logic or the development
port and determines the operating mode of the development port at
reset.
TDO
DSDO
Low
G17
Output
Output serial data for either the scan chain logic or for the
development port.
TRST
Pulled up
G19
Input
Reset for the scan chain logic. If JTAG is not used, connect TRST to
ground. If JTAG is used, connect TRST to PORESET. In case
PORESET logic is powered by the keep-alive power supply
(KAPWR), connect TRST to PORESET through a diode (anode
connected to TRST and cathode to PORESET).
SPARE[1-4]
Hi-Z
B7, H18,
V15, H4
No-connect
Spare signals—Not used on current chip revisions. Leave
unconnected.
Power Supply
See
Figure 4
Power
V
DDL
—Power supply of the internal logic.
V
DDH
—Power supply of the I/O buffers and certain parts of the clock
control.
V
DDSYN
—Power supply of the PLL circuitry.
KAPWR—Power supply of the internal OSCM, RTC, PIT, DEC, and
TB.
V
SS
—Ground for circuits, except for the PLL circuitry.
V
SSSYN
, V
SSSYN1
—Ground for the PLL circuitry.
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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