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參數(shù)資料
| 型號： | TS68HC901CP5 |
| 廠商： | 意法半導體 |
| 英文描述： | HCMOS MULTI-FUNCTION PERIPHERAL |
| 中文描述： | HCMOS多功能外設 |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 369K |
| 代理商： | TS68HC901CP5 |
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7
0
TSR
(2Dh)
BE
UE
AT
END
B
H
L
TE
Figure 19 :
USART errorconditions are only valid for each character boundary. When theUSART performs block
data transfers by using the DMAhandshake line RR (receiver ready) and TR (transmitter ready), errors
must be saved and checked at the end of a block. This is accomplished by enabling the error channel
for thereceiver ortransmitter and by masking interrupts for this channel. Once the transfer is complete,
interrupt pending register A is read. Any pending receiver or transmitter error indicates an error in the
data transfer.
BE
BufferEmpty. Thisbit is setwhen thewordinthe transmit buffer is transferred to thetransmit
shiftregister. This bitis cleared when the transmit buffer is reloaded by writing to the USART
data register (UDR).
SET : Transmit buffer contents transferred to transmit shift register
CLEARED : Transmit buffer written
Underrun Error. Thisbitissetwhen thewordinthetransmit shiftregisterhasbeentransmitted
before a new word is loaded into the transmit buffer. This bit is cleared by reading theTSR
or bydisabling thetransmitter. Thisbit doesnot need to beclearedbefore writing tothe UDR.
SET : Transmit shift register contents transmitted before transmit buffer written
CLEARED : Transmitter status register read or Transmitter disabled
Auto-Turnaround. When this bit is set, the receiver will be enabled automatically after the
transmitter has been disabled and thelast character being transmitted is completed.
SET : MPU writes a one
CLEARED : Transmitter disabled
END
End of Transmission. Whenthe transmitter is disabledwhilea character isbeing transmitted,
theENDwillbesetafterthecharacter transmissioniscomplete. Ifnoword isbeing transmitted
when the transmitter is disabled, the ENDbit will be set immediately. The END bit is cleared
by reenabling the transmitter.
SET : Transmitter disabled
CLEARED : Transmitter enabled
UE
AT
B
Break. This bit has no function in the
synchronous character format. In the
asynchronous character format, when
this bit is set to a one, a break will be
transmittedupon thecompletion ofthe
transmission of any word in thetrans-
mit shift register. A break consists of an all zero data word with no stop bit. When this bit is
cleared bysoftware,thebreakindicationwillceaseandnormaltransmission willresume. Note
that when B is set,BE cannot be set.
SET : MPU writes a one
CLEARED : MPU writes a zero
H, L
High and Low. These control bits configure the transmitter output (SO) when the transmitter
is disabled. These bits also force the transmitter output after the transmitter is enabled until
END is cleared.
Loopback modeinternally connects thetransmitter outputtothe receiverinput and the trans-
mitter clock to the receiver clock internally. The receiver clock (RC) and the serial input (SI)
are not used. When the transmitter is disabled, SO is forced high.
SET : MPU writes a one
H
0
0
1
1
L
0
1
0
1
Output
High Impedance
LOW
High
Loopback Mode
TS68HC901
28/42
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS68HC901CP8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HCMOS MULTI-FUNCTION PERIPHERAL |
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| TS-6A1P00A | 制造商:APEM 功能描述:Joystick, Thumbstick, with Pushbutton Handle plus Limiter Plate 制造商:APEM 功能描述:THUMBSTK W/ PB HNDL + LMTR PLT 制造商:APEM 功能描述:Input Devices Thmbstick w/Pushbttn Hndl w/ LimiterPlate |
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