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參數(shù)資料
| 型號： | TS68HC901CP5 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS MULTI-FUNCTION PERIPHERAL |
| 中文描述： | HCMOS多功能外設(shè) |
| 文件頁數(shù)： | 14/42頁 |
| 文件大?。?/td> | 369K |
| 代理商： | TS68HC901CP5 |
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NESTING CMFPINTERRUPTS
In a 68000 vectored interrupt system, the CMFP is
assigned to one of seven possible interrupt levels.
Whenaninterrupt isreceived fromtheCMFP, anin-
terrupt acknowledge for that level is initiated. Once
an interrupt is recognized at a particular level, inter-
rupts at that same level or below are masked by
68000. As longas the processor’s interrupt mask is
unchanged, the 68000 interrupt structure will prohi-
bit the nesting of interrupts at the same interrupt le-
vel. However, additional interrupt requests from the
CMFP can be recognized before a previous chan-
nel’s interrupt service routine is completed by lowe-
ringthe processor’s interrupt mask to thenextlower
interrupt level within the interrupt handler.
Whennesting CMFP interrupts, it may be desirable
to permit interrupts on any CMFP channel, regar-
dless ofitspriority, to preempt or delay interrupt pro-
cessing of an earlier channel’s interrupt service re-
quest. Or, it may be desirable to only allow sub-
sequent higher priority channel interrupt requests to
supersede previously recognized lower priority in-
terrupt requests. The CMFPinterrupt structure pro-
vides this flexibility by offering two end-of-interrupt
options for vectored interrupt schemes. Note that
theend-of-interrupt modesare not activeina polled
interrupt scheme.
SELECTING THE END-OF-INTERRUPT MODE
In a vectored interrupt scheme, the CMFP may be
programmed tooperate ineithertheautomatic end-
of-interrupt mode or the software end-of-interrupt
mode. The mode is selected by writing the S bit of
the vector register (see figure 7). Whenthe S bit is
programmed to a one, the CMFP is placed in the
software end-of-interrupt mode and when the S bit
isa zero,all channels operate in the automatic end-
of-interrupt mode.
AUTOMATIC END-OF-INTERRUPT
When an interrupt vector number is passed to the
processor during an interrupt acknowledge cycle,
the corresponding channel’s interrupt pending bit is
cleared. In the automatic end-of-interrupt mode, no
further history of the interrupt remains in theCMFP.
The in-service bits of the interrupt in-service regis-
ters (ISRA and ISRB) are forced low. Subsequent
interrupts which arereceived onanyCMFPchannel
will generate an interrupt request to the processor,
evenifthe currentinterrupt’s service routine hasnot
been completed.
SOFTWARE END-OF-INTERRUPT
In thesoftwareend-of-interrupt mode, thechannel’s
associatedinterrupt pending bitiscleared and inad-
dition,the channel’s in-service bitofin-service regis-
ter A or B is set when its vector number is passed
to theprocessor duringanIACKcycle.Ahigherprio-
ritychannelmaysubsequently request interrupt ser-
viceandbeacknowledged, but as longas thechan-
nel’s in-service bit is set, no lower priority channel
may request interrupt service nor passitsvector du-
ring an interrupt acknowledge sequence.
While only higher priority channels may request in-
terruptservice, any channel canreceive an interrupt
and set its interrupt pending bit. Even the channel
whose in-service bit is setcan receivea second in-
terrupt. However, no interrupt service request is
made until its in-service bit iscleared.
The in-service bit for a particular channel can be
cleared by writing a zero to itscorresponding bit in
ISRA or ISRB and ones to all other bit positions.
Since bits in the in-service registers can only be
cleared in software and not set, writing ones to the
register does not alter their contents. ISRA and
ISRB maybe read at any time.
TS68HC901
14/42
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
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