參數(shù)資料
型號(hào)： TS68HC901CP5
廠商： 意法半導(dǎo)體
英文描述： HCMOS MULTI-FUNCTION PERIPHERAL
中文描述： HCMOS多功能外設(shè)
文件頁(yè)數(shù)： 19/42頁(yè)
文件大?。?/td> 369K
代理商： TS68HC901CP5
gle the timer output, and aninterrupt may be optio-
nally generated on the timer interrupt channel.
Note that the pulse width measured will include
counts from before the main counter was reloaded.
If the timer data register is written while the pulse is
transitioning totheactivestate,anindeterminate va-
lue may be written intothe main counter.
Once the timer is reprogrammed for another mode,
interrupts willagainoccurasnormally defined bythe
edgebit. Note thataninterrupt maybe generated as
the result of placing the timer into the pulse width
measurement mode or by reprogramming the timer
for another mode. Also, an interrupt may be gene-
rated by changing the state of the edgebit while in
thepulse width measurement mode.
EVENT COUNT MODE OPERATION
In addition to the delay mode and the pulse width
measurement mode, timers A and B may be pro-
grammed to operate in the event count mode. Like
the pulse width measurement mode, the event
count mode also requires an auxiliary input signal,
TAI or TBI, and the interrupt channels normally as-
sociated with I4 and I3 will respond to transitions on
TAI and TBI respectively. Generalpurpose lines I3
and I4 only function as I/O ports.
In the event count mode the prescaler is disabled,
allowingeachactive transitionon TAIand TBItopro-
duce a count pulse. The count pulse causes the
main counter to decrement by one. When the timer
counts through 01 (hexadecimal), a time out pulse
is generated which will cause the output signal to
toggle and may optionally produce an interrupt via
the associated timer interrupt channel. The timer’s
main counterisalsoreloaded fromthetimerdata re-
gister. To counttransitions reliably, the input signal
may only transition once every four timer clock pe-
riods. For this reason, the input signalmust have a
maximum frequency equal to one-fourth that of the
timer clock.
The active edge of the auxiliary input signal is defi-
ned by the associated interrupt channel’s edge bit.
GPIP4of theAER specifies the active edge for TAI
and GPIP3 defines the active edge for TBI. When
theedge bit is programmed to a one, a count pulse
will be generated onthe zero-to-one transitionof the
auxiliary inputsignal. When the edge bit is program-
med to a zero, a count pulse will be generated on
the one-to-zero transition. Also, note that changing
the stateoftheedge bitwhilethetimerisintheevent
count mode may produce a countpulse.
Besidesgenerating a count pulse, the active trans-
ition of the auxiliary input signal will alsoproduce an
interrupt on the I3 or I4 interrupt channel, if the in-
terrupt channel is enabled. Typically, in the event
count mode, these channels are not enabledsince
the timer isautomatically counting transitions onthe
input signal. If the interrupt channel is enabled, the
number of transitions could be counted in the inter-
rupt routine without requiring the use of the timer.
TIMER REGISTERS
Thefourtimersare programmed viathreecontrolre-
gisters and four timer data registers. Control regis-
ters TACR and TBCR and timer data registers
TADRandTBDR (refertofigure 5.1) areassociated
withtimersAandBrespectively. TimersCandDare
controlled by the control register TCDCR and the
dataregisters TCDRandTDDR (refertoFigure 13).
TIMER DATA REGISTERS
Each timer’s main counter is an 8-bit binary down
counter. Thevalueof the maincounter may be read
at anytime by reading thetimer’s data register. The
information read is the value of the counter which
was capturedon thelastlow-to-hightransition ofthe
DS pin.
The main counter is initialized by writing to the ti-
mer’s data register. If the timer is stopped, data is
loadedsimultaneouslyintoboththetimerdata regis-
ter and the main counter. If the timer data register
is written whilethetimer is enabled, the valueis not
loaded into the timer until the timer counts through
01 (hexadecimal). Writing the timer data register
while thetimeriscountingthrough01(hexadecimal)
will cause an indeterminate valueto be loaded into
the timer’smain counter. Thefour dataregisters are
shown inFigure 13.
TIMER CONTROL REGISTERS
Bitsinthe timercontrol registers selecttheoperation
mode, select the prescaler value, and disable theti-
mers. Timer control registers TACRand TBCRalso
have bits which allow the programmer to reset out-
TS68HC901
19/42
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