參數(shù)資料
型號(hào)： TS68HC901CP5
廠商： 意法半導(dǎo)體
英文描述： HCMOS MULTI-FUNCTION PERIPHERAL
中文描述： HCMOS多功能外設(shè)
文件頁(yè)數(shù)： 26/42頁(yè)
文件大小： 369K
代理商： TS68HC901CP5
SET : Incoming word received and receive buffer full
CLEARED : Receiver status register read
PE
Parity Error. This bit is set when theword transferred to the receive buffer has a parity error.
Thisbitiscleared when theword transferred tothe receivebufferdoes nothavea parityerror.
SET : Word in receive buffer has a parity error
CLEARED : Word in receive buffer does not have a parity error
FE
Frame Error. A frame error exists when a non-zero data word isnot followed by a stop bit in
the asynchronous character format. The FEbitissetwhen the word transferred tothereceive
bufferhas a frameerror. TheFEbit iscleared when theword transferred to thereceive buffer
does nothave a frame error.
SET : Word in receive buffer has a frame error
CLEARED : Word in receive buffer does not have a frame error
F/S or B
Found/Search orBreak Detect.Inthesynchronous characterformat thisbitcanbesetor clea-
red by software. When the bit is a zero, the USART receiver is placed in the search mode.
The incoming data is compared to the synchronous character register (SCR) and the word
length counter is disabled. The F/S bit will automatically be set when a match is found and
thewordlength counterwillbeenabled. Aninterrupt willalso beproduced onthereceiveerror
channel.
SET : Incoming word matches synchronous character
CLEARED : MPU writes a zero or Incoming word does not match synchronous character
In the asynchronous character format, this flag indicates a break condition. Abreak is detec-
ted when an all zero data word with no stop bit is received. The break condition continues
untila non-zero data bit is received. The 8-bit is set when theword transferred to the receive
buffer is a break indication. A break condition generates an interrupt to the processor. This
bit iscleared when a non-zero data bitis received and the break condition hasbeen acknow-
ledged by reading the RSRat least once. An end of breakinterrupt will be generated when
the bit is cleared.
SET : Word in receive buffer is a break
CLEARED : Break terminates and receiver status register read since beginning of break condition
M or CIP Match/Character in Progress. In the synchronous format, this flag indicates that a synchro-
nous character has been received. The M bit is set when the word transferred to the receive
buffermatchesthesynchronous character register.TheM bit is cleared when thewordtrans-
ferredto the receive buffer does not matchthe synchronous character register.
SET : Word transferred to receive buffer matches the synchronous character
CLEARED : Word transferred to receive buffer does not match synchronous character
In theasynchronous character format,this flag indicates that a wordisbeing assembled. The
CIP bit is set when a start bit is detected. The CIP bit is cleared when the final stop bit has
been received.
SET : Start bit is detected
CLEARED : End of word detected
SS
Synchronous Strip Enable. When this bit is a one, data words that match the synchronous
character register will not be loaded into thereceive bufferand no bufferfullcondition will be
produced. When this bit is a zero, data words that match thesynchronous character register
willbe transferred to the receive buffer and a buffer full condition will be produced.
SET : MPU writes a one
Receiver Status Register (Continued)
TS68HC901
26/42
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