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interrupt structure is not implemented, the IEI of all
CMFPsmust be tied low.
When the processor initiates an interrupt acknow-
ledge cycle by driving IACK and DS, the CMFP
whose IEI is lowmay respond with a vector number
if interrupt is pending. If this device does not have a
pending interrupt, IEO is asserted which allows the
next lower priority device to respond to the interrupt
acknowledge. When an CMFP propagates IEO, it
will not drive thedata bus nor DTACKduring the in-
terrupt acknowledge cycle. The timing for an IACK
cycle is shown infigure 23 and 24.
RESET OPERATION
The reset operation will initialize the CMFP to a
known state. The reset operation requires that the
RESET input be asserted for a minimum of two
microseconds. During a device reset condition, all
internal CMFP registers are cleared except for the
timer data registers (TADR, TBDR, TCDR and
TDDR), theUSART data register (UDR), the trans-
mitter status register (TSR) and theinterrupt vector
register. All timers are stopped and the USART re-
ceiver and transmitter are disabled. The interrupt
channels are also disabled and any pending inter-
rupts are cleared. In addition, the general purpose
interruptI/Olinesare placed inthehigh- impedance
inputmode andthe timer outputs aredriven low. Ex-
ternalCMFPsignalsarenegated.Theinterrupt vec-
tor register is initialized to a 0Fh.
NON MULTIPLEXED MODE
In thismode, the MPX inputmustbe setto zero, and
the TS68HC901 can be used with a 68000 proces-
sortypeor a 6800 processor type. Refer to figure21
to 24for the electrical characteristics.
With a6800 processor typethe DSpinisconnected
to the E signal of the processor, the DTACK signal
is not used and theCLK must be zeroed.
MULTIPLEXED MODE
The CMFPcan be used either on a MOTOROLAor
INTELbustype.InthiscasetheMPXpinisconnec-
ted to Vcc. The table page 4 gives thesignification
ofthedifferent signals used. Adummy accessto the
TS68HC901 hastobe done beforeanyvalidaccess
in orderto set up the internal logicof sampling.
TS68HC901
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