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參數(shù)資料
| 型號： | TS68HC901CFN8 |
| 廠商： | 意法半導體 |
| 英文描述： | HCMOS MULTI-FUNCTION PERIPHERAL |
| 中文描述： | HCMOS多功能外設 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大小： | 369K |
| 代理商： | TS68HC901CFN8 |
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Figure 3 : PDIP Pin connection
PIN DESCRIPTION
GND :
Ground
V
CC
:
+5 volts(
±
5%)
R/W :
Read/Write (input). This input defines a
data transfert as a Read (High) or Write
(Low) cycle. This signal is used as WR
with an Intelprocessor type.
DTACK : This output signals the completion of the
operation phase ofabuscycleto thepro-
cessor. If the bus cycle is a processor
read, the CMFP asserts DTACK to indi-
cate thattheinformation on theData bus
is valid.If the bus cycle is a processor to
the CMFP, DTACK acknowledges the
acceptance of the data by the CMFP.
DTACKwill beassertedonlybyanCMFP
that has CS or IAK (and IEI) asserted.
This signal is not used with a 6800pro-
cessortype.
Figure 4 : PLCC Pin connection
Pin
MOTOROLA
6800 Type
MOTOROLA
Multiplexed
INTEL
48
47
1
35
CS
E
R/W
V
SS
CS
DS
R/W
AS
CS
RD
WR
ALE
CS :
Chip Select (input, active low). CS is u-
sed to select the TS68HC901 CMFPfor
accesses to the internal registers. CS
and IACKmust not be asserted at the
same time.
Data Stobe (input, active low).This Input
is part of the internal chip select and in-
terrupt acknowledge functions.
The CMFP must be located on thelower
portion of the 16-bitdata-bus so that the
vector number passed to the processor
during an interrupt acknowledge cycle
willbe located inthe low byte of the data
word.Asa result,DS mustbe connected
to the processor’s lower data strobe if
vectored interrupt are to be used. Note
that this forces all registers to be located
atoddaddresses and latches data onthe
rising edge forwrites. This signal isused
as RD with an Intel processor type.
DS :
TS68HC901
4/42
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