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參數(shù)資料
| 型號： | TS68HC901CFN8 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS MULTI-FUNCTION PERIPHERAL |
| 中文描述： | HCMOS多功能外設(shè) |
| 文件頁數(shù)： | 12/42頁 |
| 文件大小： | 369K |
| 代理商： | TS68HC901CFN8 |
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INTERRUPTCONTROL REGISTERS
CMPFinterrupt processing ismanaged by the inter-
rupt enable registers A and B, interrupt pending re-
gisters A and B, and interrupt mask registers A and
B. These registers allow the programmer to enable
or disable individual interrupt channels, mask indi-
vidual interrupt channels, andaccesspending inter-
ruptstatus information. In-service registers Aand B
allow interrupts tobe nestedasdescribed hereafter.
The interrupt control registers are shown in fig-
ure 10.
INTERRUPTENABLE REGISTERS
Theinterrupt channels are individually enabled ordi-
sabled by writing a one or zero, respectively, to the
appropriate bit of interrupt enable register A(IERA)
or interrupt enable register B (IERB). Theprocessor
may read these registers at anytime.
When a channel is enabled, interrupts received on
the channel will be recognized by the CMFP and
IRQwillbeasserted tothe processor, indicating that
interrupt service isrequired. Onthe otherhand, adi-
sabled channel is completely inactive; interrupts re-
ceived on the channel are ignored by the CMFP.
Writing a zero to a bit of interrupt enable register A
orBwillcause thecorresponding bitofinterrupt pen-
dingregisterAorBtobe cleared. This willterminate
allinterrupt service requests for the channel and al-
so negate IRQ, unless interrupts are pending from
other sources. Disabling a channel, however, does
not affect the corresponding bit in interrupt in-ser-
vice registers A orB. So, if the CMFPis in thesoft-
ware end-of-interrupt mode and an interrupt is in
service when a channel will remain set until cleared
by software.
INTERRUPT PENDING REGISTERS
When an interrupt is received on an enabled chan-
nel, the corresponding interrupt pending bit is set in
interrupt pending register A or B (IPRA or IPRB). In
a vectored interrupt scheme, this bit will be cleared
when the processor acknowledges the interrupting
channelandthe CMFPresponds witha vectornum-
ber. In a polled interrupt system, the interrupt pen-
ding registers must be read to determine theinter-
ruptingchannel andthen theinterrupting pending bit
is cleared by the interrupt handling routine without
performing aninterrupt acknowledge sequence.
A singlebit of the interrupt pending registers is clea-
red insoftwareby writing onestoallbit positionsex-
cept the bit to be cleared. Note that writing ones to
IPRA andIPRB has no effect on the contents of the
register. A single bit of the interrupt pending regis-
ters isalso clearedwhenthecorresponding channel
is disabled by writing a zero to the appropriate bit of
IERA or IERB.
INTERRUPT MASK REGISTERS
Interrupts are masked for a channel by clearing the
appropriate bit in interrupt mask register A or B(IM-
RA or IMRB). Even though an enabled channel is
masked, the channel will recognize subsequent in-
terrupts and set its interrupt pending bit. However,
the channel is prevented from requesting interrupt
service(IRQ to the processor) as long as the mask
bit for that channel is cleared.
If achannelisrequestinginterruptserviceat thetime
that its corresponding bit in IMRA or IMRB is clea-
red, the request will cease and IRQ will be negated,
unless another channel is requesting interrupt ser-
vice.Later, whenthemaskbit isset,anypending in-
terrupt on the channel will be processed according
to the channel’s assigned priority. IMRA and IMRB
may be read at anytime.
TS68HC901
12/42
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