參數(shù)資料
型號： TS68HC901CFN8
廠商： 意法半導體
英文描述： HCMOS MULTI-FUNCTION PERIPHERAL
中文描述： HCMOS多功能外設
文件頁數(shù)： 15/42頁
文件大?。?/td> 369K
代理商： TS68HC901CFN8
GENERAL PURPOSE INPUT/OUTPUT
INTERRUPTPORT
Thegeneral purpose interrupt input/output (I/O)port
(GPIP) provides eight I/O lines (I0 through I7) that
may be operated as either inputs or outputs under
software control. In addition, theselines mayoptio-
nally generate an interrupt oneithera positive trans-
ition or negative transition of the input signal. The
flexibility of theGPIPallows itto beconfigured as an
8-Bit I/0 port or for bit I/O. Since interrupts are en-
abled on a bit-by-bit basis, a subset of the GPIP
could be programmed as handshake lines or the
port could be connected to as many as eight exter-
nal interrupt sources, which wouldbe prioritized by
theCMFP interrupt controller for interrupt service.
6800 INTERRUPTCONTROLLER
The CMFP interrupt controller is particularly useful
ina system which hasmany6800-type devices. Ty-
pically, in a vectored 68000 system, 6800-type pe-
ripherals use the autovector which corresponds to
their assigned interrupt level since theydo notpro-
vide a vector number in response to an AC cycle.
The autovector interrupt handler must then poll all
6800-type devices at that interrupt level to deter-
mine which device is requesting service. However,
by tying the IRQ output from a 6800-type device to
the general purpose I/O interrupt port (GPIP) of a
CMFP, a unique vector number will be provided to
the processor during an interrupt acknowledge cy-
cle. This interrupt structure will significantly reduce
interrupt latencyfor6800-type devices andotherpe-
ripheral devices which do not support vector-by-de-
vice.
GPIP CONTROL REGISTERS
The GPIPis programmed viathreecontrol registers
shown in figure 11.These registers control the data
direction provideuseraccesstotheport, andspecify
the active edge for each bit of the GPIP which will
produce an interrupt. These registers are described
in detail in the following paragraphs.
GPIP DATA REGISTER
The general purpose I/O data register is used to in-
put or output data to the port. When data is written
to theGPIP data register, those pins which are de-
fined as inputs will remain in the high-impedance
state.Pins which aredefined asoutputs willassume
the state (high or low) of their corresponding bit in
the data register. When the GPIP is read, data will
be passeddirectly from thebits of thedata register
for pinswhicharedefinedasoutputs.Datafrompins
defined as inputs will come from the input buffers.
ACTIVE EDGE REGISTER
The active edge register (AER) allows each of the
GPIP lines to produce an interrupt on either a one-
to-zeroor azero-to-one transition.Writing azerothe
appropriate edge bit of the active edge register
causestheassociatedinput to generate an interrupt
on the one-to-zero transition. Writing a one to the
edge bitwill produce aninterrupt onthe zero-to-one
transition of thecorresponding GPIP line.
TS68HC901
15/42
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