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參數(shù)資料
| 型號： | TS68HC901CFN8 |
| 廠商： | 意法半導體 |
| 英文描述： | HCMOS MULTI-FUNCTION PERIPHERAL |
| 中文描述： | HCMOS多功能外設 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大小： | 369K |
| 代理商： | TS68HC901CFN8 |
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RS1-RS5:
(A1-A5)
Register Address Bus (inputs). The ad-
dress bus is used to address one of the
internal registers during a read or write
cycle.
Data Bus (bi-directional, tri-stateable).
This bus is used to receive data from or
transmit data to the MFP’s internal regis-
ters during a processor read or write cy-
cle. During an interrupt acknowledge cy-
cle, thedata bus isused to pass a vector
number to theprocessor. Sincethe MFP
is an 8-bit peripheral, the MFP could be
locatedon either theupper or lower por-
tion of the 16-bit data bus (even or odd
address). However, during an interrupt
acknowledge cycle, the vector number
passedto theprocessor must belocated
in thelow byte of the data word. As a re-
sult, D0-D7 of the MFP must be connec-
ted to the low eight bits of the processor
data bus, placing MFP registers at odd
addresses if vectoredinterrupt are to be
used.
The clock input is a single-phase TTL
compatible signal used for internal ti-
ming . Thisinput should not be gated off
at any time and must conform to mini-
mum and maximum pulse width times.
The clock is not necessarily the system
clock in frequency nor phase. When the
bus is multiplexed (MPX=1), an address
strobe signal is connected to this pin. In
the nonmultiplexed mode (MPX=0), this
input is connected to the system clock
when used with a 68000 processor type
or to V
SS
(0V
DC
) when used with a 6800
processor type.
RESET : Device reset. (input, active low). Reset
disables the USART receiver and trans-
mitter, stops all timers and forces the ti-
mer outputs low, disables all interrupt
channels and clears any pending inter-
rupts.The GeneralPurpose Interrupt/I/O
lines will be placed in the tri-state input
mode. All internal registers (except theti-
mer,USART data registers, and transmit
status register) will be cleared.
MPX :
This input selects thedata bus mode:
MPX = 0 : non multiplexed mode
MPX=1:multiplexed mode.Theregister
select lines RS1-RS5 and the data bus
D0-D7 are multiplexed. An address
strobemustbeconnected totheCLKpin.
D0-D7 :
CLK :
IRQ :
Interrupt Request (output, active low, o-
pen drain). This output signals the pro-
cessor that an interrupt is pending from
the CMFP. These are 16 interrupt chan-
nels that can generate an interrupt re-
quest. Clearing the interrupt pendingre-
gisters (IPRA and IPRB) or clearing the
interrupt mask registers (IMRA and
IMRB) willcause IRQto be negated. IRQ
willalso benegated astheresult of anin-
terrupt acknowledge cycle, unless addi-
tional interrupts are pending in the
CMFP. Refer to paragraph INTER-
RUPTS for further information.
Interrupt Acknowledge (input, active
low). IACK is used to signal the
TS68HC901 that the CPU is acknow-
ledging an interrupt. CS and IACk must
not be asserted at the same time.
Interrupt Enable In (input,active low). IEI
isused to signal theTS68HC901 that no
higher priority device is requesting inter-
rupt service.
Interrupt Enable Out (output, active low).
IEO is used to signal lower priority peri-
pherals that neither the TS68HC901 nor
another higher priority peripheral is re-
questing interrupt service.
General Purpose Interrupt I/O lines.
These lines may be used as interrupt in-
puts and/or I/Olines.Whenused asinter-
rupt inputs, their active edge is program-
mable. Adata direction register isusedto
define which lines are to be Hi-Z inputs
and which lines are to be push-pull TTL
compatible outputs.
SerialOutput. This is the output of the U-
SART transmitter.
Serial Input. This is the input to the U-
SART receiver.
Receiver Clock. This input controls the
serial bit rate of the USARTreceiver.
TransmitterClock.This input controls the
serial bit rate of the USARTtransmitter.
Receiver Ready. (output, active low)
DMA output for receiver, which reflects
the status of Buffer Full in port number
15.
Transmitter Ready. (output, active low)
DMA output for transmitter, which re-
flects the status of Buffer Empty in port
number 16.
IACK :
IEI :
IEO :
I0-I7 :
SO :
SI :
RC :
TC :
RR :
TR :
TS68HC901
5/42
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