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| 型號： | TMS320WP010PZA |
| 英文描述： | Cell-Phone Circuit |
| 中文描述： | 手機電路 |
| 文件頁數(shù)： | 36/132頁 |
| 文件大小： | 1707K |
| 代理商： | TMS320WP010PZA |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
DSP CPU core
The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by
maintaining two separate memory bus structures
—
program and data
—
for full-speed execution. This multiple
bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a
four-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. See
the functional block diagram of the 240xA DSP CPU for more information.
TMS320x240xA instruction set
The x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The TMS320x240xA instruction set provides four basic memory-addressing modes: direct, indirect, immediate,
and register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0
–
AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
scan-based emulation
TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware-
development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The x240xA DSPs do not include boundary scan. The
scan chain of these devices is useful for emulation function only.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320-XDS100-V2 | 功能描述:仿真器/模擬器 USB JTAG DONGLE XDS100V2 TMS320 RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| TMS320-XDS100-V3 | 功能描述:仿真器/模擬器 XDS100V3 DSP / ARM HIGH SPEED USB JTAG RoHS:否 制造商:Blackhawk 產(chǎn)品:System Trace Emulators 工具用于評估:C6000, C5000, C2000, OMAP, DAVINCI, SITARA, TMS470, TMS570, ARM 7/9, ARM Cortex A8/R4/M3 用于:XDS560v2 |
| TMS32AV110PBM | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMS32C31PQA40 | 制造商:Texas Instruments 功能描述: |
| TMS32C5402PGER10G4 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Tape & Reel Version 5402PGE100 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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