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| 型號： | TMS320WP010PZA |
| 英文描述： | Cell-Phone Circuit |
| 中文描述： | 手機(jī)電路 |
| 文件頁數(shù)： | 21/132頁 |
| 文件大?。?/td> | 1707K |
| 代理商： | TMS320WP010PZA |
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SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
W/R
/ IOPC0
W/R
19
Write/Read qualifier or GPIO. This is an inverted
R/W signal useful for zero-wait-state memory
interface. It is normally low, unless a memory write
operation is performed.
See Table 12, Port C
section, for reset note regarding LF2406A and
LF2402A.
(
↑
)
Read-enable strobe. Read-select indicates an
active, external read cycle. RD is active on all
external program, data, and I/O reads. RD is
placed in the high-impedance state.
IOPC0
19
14
14
RD
93
WE
89
Write-enable strobe. The falling edge of WE
indicates that the device is driving the external
data bus (D15
–
D0). WE is active on all external
program, data, and I/O writes. WE is placed in the
high-impedance state.
STRB
96
External memory access strobe. STRB is always
high unless asserted low to indicate an external
bus cycle. STRB is active for all off-chip
accesses. STRB is placed in the high-impedance
state.
READY
120
READY is pulled low to add wait states for
external accesses. READY indicates that an
external device is prepared for a bus transaction
to be completed. If the device is not ready, it pulls
the READY pin low. The processor waits one
cycle and checks READY again. Note that the
processor performs READY-detection if at least
one software wait state is programmed. To meet
the external READY timings, the wait-state
generator control register (WSGR) should be
programmed for at least one wait state.
(
↑
)
MP/MC
118
Microprocessor/Microcomputer mode select. If
this pin is low during reset, the device is put in
microcomputer mode and program execution
begins at 0000h of internal program memory
(Flash EEPROM). A high value during reset puts
the device in microprocessor mode and program
execution begins at 0000h of external program
memory. This line sets the MP/MC bit (bit 2 in the
SCSR2 register).
(
↓
)
Bold, italicized pin names
indicate pin function after reset.
GPIO
–
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
–
Internal pullup
↓
–
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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