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參數(shù)資料
| 型號： | TMS320FN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Adjustable 1.24-16V ±0.5% Tolerance, 0.05-20mA Shunt Regulator; Package: TO-92 (TO-226) 5.33mm Body Height; No of Pins: 3; Container: Tape and Reel; Qty per Container: 2000 |
| 中文描述： | 第二代數(shù)字信號處理器 |
| 文件頁數(shù)： | 88/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320FN |
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6.5.2
Test Load Circuit
Transmission Line
4.0 pF
1.85 pF
Z0 = 50
(Α)
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42
3.5 nH
Device Pin
(B)
6.5.3
Device Clock Table
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
This test load circuit is used to measure all switching characteristics provided in this document.
A.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
B.
Figure 6-3. 3.3-V Test Load Circuit
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs.
Table 6-5
lists the cycle times of various clocks.
Table 6-5. TMS320x280x Clock Table and Nomenclature
MIN
28.6
20
10
NOM
MAX
UNIT
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
t
c(OSC)
, Cycle time
Frequency
t
c(CI)
, Cycle time
Frequency
t
c(SCO)
, Cycle time
Frequency
t
c(XCO)
, Cycle time
Frequency
t
c(HCO)
, Cycle time
Frequency
t
c(LCO)
, Cycle time
Frequency
t
c(ADCCLK)
, Cycle time
Frequency
50
35
On-chip oscillator
clock
250
100
500
100
2000
100
XCLKIN
(1)
4
10
2
10
0.5
10
SYSCLKOUT
XCLKOUT
20
(3)
50
(3)
40
(3)
25
(3)
HSPCLK
(2)
100
10
LSPCLK
(2)
100
80
ADC clock
12.5
(1)
(2)
(3)
This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 100 MHz.
88
Electrical Specifications
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