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參數(shù)資料
| 型號： | TMS320FN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Adjustable 1.24-16V ±0.5% Tolerance, 0.05-20mA Shunt Regulator; Package: TO-92 (TO-226) 5.33mm Body Height; No of Pins: 3; Container: Tape and Reel; Qty per Container: 2000 |
| 中文描述： | 第二代數(shù)字信號處理器 |
| 文件頁數(shù)： | 29/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320FN |
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3.2.6
M0, M1 SARAMs
3.2.7
L0, L1, H0 SARAMs
3.2.8
Boot ROM
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
NOTE
The F2808/F2806/F2801 Flash and OTP wait states can be configured by the application.
This allows applications running at slower frequencies to configure the flash to use fewer
wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the
TMS320x280x System Control and Interrupts Reference Guide
(literature number
SPRU712).
All 280x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to
execute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.
The F2808 contains an additional 16K x 16 of single-access RAM, divided into 3 blocks (L0-4K, L1-4K,
H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K,
L1-4K). The F2801/UCD9501 contain an additional 4K x 16 of single-access RAM (L0-4K). Each block
can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to both program
and data space.
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in
math related algorithms.
Table 3-5. Boot Mode Selection
GPIO18
SPICLKA
SCITXDB
1
GPIO29
SCITXDA
GPIO34
MODE
DESCRIPTION
Boot to Flash
Jump to Flash address 0x3F 7FF6
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
Load a data stream from SCI-A
Load from an external serial SPI EEPROM on SPI-A
Load data from an external EEPROM at address 0x50 on
the I2C bus
Call CAN_Boot to load from eCAN-A mailbox 1.
Jump to M0 SARAM address 0x00 0000.
Jump to OTP address 0x3D 7800
Load data from GPIO0 - GPIO15
1
1
SCI-A Boot
SPI-A Boot
I2C Boot
1
1
1
1
0
0
0
1
0
eCAN-A Boot
Boot to M0 SARAM
Boot to OTP
Parallel I/O Boot
0
0
0
0
1
1
0
0
1
0
1
0
Functional Overview
29
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