參數(shù)資料
型號(hào): TMS320C82GGP-50
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-Bit Digital Signal Processor
中文描述: 32位數(shù)字信號(hào)處理器
文件頁數(shù): 87/132頁
文件大?。?/td> 1707K
代理商: TMS320C82GGP-50
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
87
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
LPM2 wakeup timings
switching characteristics over recommended operating conditions (see Figure 32)
PARAMETER
MIN
MAX
UNIT
td(PDP-PWM)HZ
Delay time, PDPINTx low to PWM high-impedance state
12
ns
td(INT)
Delay time, INT low/high to interrupt-vector fetch
10tc(CO)
ns
timing requirements (see Figure 32)
MIN
MAX
UNIT
t(PDP WAKE)
Pulse duration PDPINTx input low
Pulse duration, PDPINTx input low
if bit 6 of SCSR2 = 0
6tc(CO)
12tc(CO)
ns
tw(PDP-WAKE)
if bit 6 of SCSR2 = 1
tp
PLL lock-up time
4096tc(CI)
cycles
This is different from 240x devices.
PWM
PDPINTx
CLKOUT
tw(PDP
WAKE)
td(PDP-PWM)HZ
CPU Status
Interrupt Vector
§
or
Next Instruction
td(INT)
XTAL1
Oscillator Disabled
CLKIN
tp
tOSC
CPU IDLE State (LPM2)
tOSC is the oscillator start-up time.
CLKOUT frequency after LPM2 wakeup will be the same as that upon entering LPM2 (x4 shown as an example).
§
PDPINTx interrupt vector, if PDPINTx interrupt is enabled.
If PDPINTx interrupt is disabled.
Figure 32. LPM2 Wakeup Using PDPINTx
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