參數(shù)資料
型號： TMS320C82GGP-50
元件分類： 數(shù)字信號處理
英文描述： 32-Bit Digital Signal Processor
中文描述： 32位數(shù)字信號處理器
文件頁數(shù)： 110/132頁
文件大?。?/td> 1707K
代理商： TMS320C82GGP-50
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
110
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
TYP
10
MAX
15
UNIT
mA
VCCA = 3.3 V
ICCA
Analog supply current
VCCA = VREFHI = 3.3 V
PLL or OSC power
down
1
A
IADREFHI
VREFHI input current
0.75
1.5
mA
IADCIN
Analog input leakage
1
A
Cai
Analog input capacitance
Typical capacitive load on
Ty ical ca acitive load on
analog input pin
Non-sampling
10
pF
Sampling
30
td(PU)
Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10
s
ZAI
Analog input source impedance
Analog input source impedance needed for
conversions to remain within specifications at min
tw(SH)
53
10
Zero-offset error
2
LSB
Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB
size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
E
DNL
and E
INL
for LF2407A/LF2406A/LF2403A/LF2402A
PARAMETER
DESCRIPTION
CLKOUT
MIN
MAX
UNIT
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value
30 MHz
2
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
30 MHz
2
LSB
Test conditions: VREFHI = VCCA, VREFLO = VSSA
E
DNL
and E
INL
for LC2406A/LC2404A
PARAMETER
DESCRIPTION
CLKOUT
MIN
MAX
UNIT
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value
40 MHz
2
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
40 MHz
2
LSB
Test conditions: VREFHI = VCCA, VREFLO = VSSA
E
DNL
and E
INL
for LC2402A
PARAMETER
DESCRIPTION
CLKOUT
30 MHz
MIN
MAX
UNIT
LSB
EDNL
Differentialnonlinearity error
Differential nonlinearity error
Difference between the actual step width
Difference between the actual ste width
and the ideal value
2
40 MHz
2
§
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
30 MHz
2
LSB
40 MHz
2
§
LSB
Test conditions: VREFHI = VCCA, VREFLO = VSSA
§
At 40 MHz CLKOUT, an
“
acquisition time window
”
of 4 clock cycles must be used.
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