參數(shù)資料
型號： TMS320C82GGP-50
元件分類： 數(shù)字信號處理
英文描述： 32-Bit Digital Signal Processor
中文描述： 32位數(shù)字信號處理器
文件頁數(shù)： 32/132頁
文件大?。?/td> 1707K
代理商： TMS320C82GGP-50
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
device reset and interrupts
The TMS320x240xA software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types
of interrupt sources.
Reset
(hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The LF240xA devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
Hardware-generated interrupts
are requested by external pins or by on-chip peripherals. There are two
types:
–
External interrupts
are generated by one of four external pins corresponding to the interrupts XINT1,
XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the
CPU
’
s interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
–
Peripheral interrupts
are initiated internally by these on-chip peripheral modules: event manager A,
event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in
each peripheral and by the CPU
’
s IMR, which can mask each maskable interrupt line at the DSP core.
Software-generated interrupts
for the LF240xA devices include:
–
The INTR instruction.
This instruction allows initialization of any LF240xA interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
–
The NMI instruction.
This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. 240xA devices do not have the NMI hardware signal, only
software activation is provided.
–
The TRAP instruction.
This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does
not
disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
–
An emulator trap.
This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1
–
INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the 240xA peripherals and are grouped to
share the six core level interrupts. Figure 8 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 8) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. LF240xA devices have interrupts identical to those of the F24x devices and should be completely
code-compatible. 240xA devices also have peripheral interrupts identical to those of the F24x
–
plus additional
interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt
grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.
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