參數(shù)資料
型號: TMS320C82GGP-50
元件分類: 數(shù)字信號處理
英文描述: 32-Bit Digital Signal Processor
中文描述: 32位數(shù)字信號處理器
文件頁數(shù): 103/132頁
文件大?。?/td> 1707K
代理商: TMS320C82GGP-50
SPRS145G
JULY 2000
REVISED FEBRUARY 2002
103
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
external memory interface
write
timings
switching characteristics over recommended operating conditions for an external memory
interface write at 40 MHz [H = 0.5t
c(CO)
] (see Figure 45)
PARAMETER
MIN
MAX
UNIT
td(COH-CNTL)
td(COH-CNTH)
td(COH-A)W
td(COH-RWL)
Delay time, CLKOUT high to control valid
4
ns
Delay time, CLKOUT high to control inactive
5
ns
Delay time, CLKOUT high to address valid
10
ns
Delay time, CLKOUT high to R/W low
6
ns
td(COH-RWH)
Delay time, CLKOUT high to R/W high
6
ns
td(COL-WL)
Delay time, CLKOUT low to WE strobe active low
6
ns
td(COL-WH)
Delay time, CLKOUT low to WE strobe inactive high
6
ns
ten(D)COL
Enable time, data bus driven from CLKOUT low
3
ns
td(COL-SL)
Delay time, CLKOUT low to STRB active low
6
ns
td(COL-SH)
Delay time, CLKOUT low to STRB inactive high
6
ns
td(WRN)
Delay time, W/R going low to R/W rising
5
ns
th(A)COLW
tsu(A)W
tsu(D)W
th(D)W
Hold time, address valid after CLKOUT low
5
ns
Setup time, address valid before WE strobe active low
H
9
ns
Setup time, write data before WE strobe inactive high
2H
17
ns
Hold time, write data after WE strobe inactive high
2
ns
tdis(W-D)
Disable time, data bus high impedance from WE high
5
ns
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