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參數(shù)資料
| 型號： | TMS320C241 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 20/66頁 |
| 文件大?。?/td> | 803K |
| 代理商： | TMS320C241 |
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TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt request structure (continued)
Table 5.’C242 Interrupt Source Priority and Vectors (Continued)
INTERRUPT
NAME
OVERALL
PRIORITY
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
POSITION
IN
PIRQRx
AND
PIACKRx
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
MASK-
ABLE
SOURCE
PERIPHERAL
MODULE
DESCRIPTION
Reserved
30
INT5
000Ah
Reserved
31
ADCINT
32
1.12
0004h
Y
ADC
ADC interrupt
(low-priority)
XINT1
33
INT6
000Ch
1.13
0001h
Y
External
Interrupt Logic
External interrupt pins
(low-priority mode)
XINT2
34
1.14
0011h
Y
External
Interrupt Logic
External interrupt pins
(low-priority mode)
Reserved
000Eh
N/A
Y
CPU
Analysis interrupt
TRAP
N/A
0022h
N/A
N/A
CPU
TRAP instruction
Phantom
Interrupt
Vector
N/A
N/A
0000h
N/A
CPU
Phantom interrupt
vector
INT8 through
INT16
N/A
0010h through
0020h
N/A
N/A
CPU
Software
Interrupt
Vectors
INT20 through
INT31
Refer to the TMS320C24x CPU System and Instruction Set, Volume 1(SPRU160); and the TMS320F243,F241,C242 DSP Controllers System
and Peripherals User’s Guide Volume 2 (SPRU276) for more information.
N/A
00028h through
0603Fh
N/A
N/A
CPU
interrupt acknowledge
When the CPU asserts its interrupt acknowledge, it simultaneously puts a value on the memory interface
program address bus, which corresponds to the CPU interrupt being acknowledged (it does this because it is
fetching the CPU interrupt vector from program memory, each INT has a vector stored in a dedicated program
memory address). This value is shown in Table 5, column 3, CPU Interrupt and Vector Address. The PIE
controller uses the CPU interrupt acknowledge to generate its internal signals to clear the current interrupt
request.
interrupt vectors
When the CPU receives an interrupt request (INT), it does not know which peripheral PIRQ caused the INT
request. To enable the CPU to distinguish among the PIRQs, a unique interrupt vector is generated in response
to a CPU interrupt acknowledge signal. This vector (PIV) is loaded into the Peripheral Interrupt Vector Register
(PIVR) in the PIE controller. The CPU reads this PIV vector value from PIVR and branches to the respective
Interrupt Service Routine (SISR). The PIVs are all implemented as hard-coded values on the ’C242, according
to Table 5, column 5.
In effect, there are two vector tables: a CPU vector table and a user-specified peripheral vector table. The CPU’s
vector table, which starts at 0000h, is used to get to the General Interrupt Service Routine (GISR) in response
to a CPU interrupt request (INT). A user-specified peripheral vector table is employed to get to the
Event-Specific Interrupt Service Routine (SISR), corresponding to the event which caused the peripheral
interrupt request (PIRQ). The code in the GISR should read the Peripheral Interrupt Vector Register (PIVR) after
saving any necessary context, and use this value PIV to generate a branch to the SISR. There is one SISR for
every interrupt request from a peripheral to the interrupt controller. The SISR performs the actions required in
response to the peripheral interrupt request.
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