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TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt request structure (continued)
Table 5. ’C242 Interrupt Source Priority and Vectors
INTERRUPT
NAME
OVERALL
PRIORITY
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
POSITION IN
PIRQRx AND
PIACKRx
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
MASK-
ABLE
SOURCE
PERIPHERAL
MODULE
DESCRIPTION
Reset
1
RSN
0000h
N/A
N
RS pin,
Watchdog
Reset from pin, watchdog
timeout
Reserved
2
–
0026h
N/A
N
CPU
Emulator Trap
NMI
3
NMI
0024h
N/A
N
Nonmaskable
Interrupt
Nonmaskable interrupt
PDPINT
4
0.0
0020h
Y
EV
Power device protection
interrupt pin
ADCINT
5
0.1
0004h
Y
ADC
ADC interrupt in
high-priority mode
XINT1
6
0.2
0001h
Y
External
Interrupt Logic
External interrupt pins in
high priority
XINT2
7
INT1
0002h
0.3
0011h
Y
External
Interrupt Logic
External interrupt pins in
high priority
Reserved
8
RXINT
9
0.5
0006h
Y
SCI
SCI receiver interrupt in
high-priority mode
TXINT
10
0.6
0007h
Y
SCI
SCI transmitter interrupt
in high-priority mode
Reserved
11
Reserved
12
CMP1INT
13
0.9
0021h
Y
EV
Compare 1 interrupt
CMP2INT
14
0.10
0022h
Y
EV
Compare 2 interrupt
CMP3INT
15
0.11
0023h
Y
EV
Compare 3 interrupt
TPINT1
16
INT2
0004h
0.12
0027h
Y
EV
Timer 1 period interrupt
TCINT1
17
0.13
0028h
Y
EV
Timer 1 PWM interrupt
TUFINT1
18
0.14
0029h
Y
EV
Timer 1 underflow
interrupt
TOFINT1
19
0.15
002Ah
Y
EV
Timer 1 overflow interrupt
TPINT2
20
1.0
002Bh
Y
EV
Timer 2 period interrupt
TCINT2
21
INT3
0006h
1.1
002Ch
Y
EV
Timer 2 PWM interrupt
TUFINT2
22
1.2
002Dh
Y
EV
Timer 2 underflow
interrupt
TOFINT2
23
1.3
002Eh
Y
EV
Timer 2 overflow interrupt
CAPINT1
24
INT4
0008h
1.4
0033h
Y
EV
Capture 1 interrupt
CAPINT2
25
1.5
0034h
Y
EV
Capture 2 interrupt
CAPINT3
26
1.6
0035h
Y
EV
Capture 3 interrupt
Reserved
27
RXINT
28
INT5
000Ah
1.8
0006h
Y
SCI
SCI receiver interrupt
(low-priority mode)
TXINT
29
1.9
0007h
Y
SCI
SCI transmitter interrupt
(low-priority mode)
A