參數(shù)資料
型號(hào): TMS320C241
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 49/66頁(yè)
文件大?。?/td> 803K
代理商: TMS320C241
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
low-power mode timings
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 19, Figure 20, and Figure 21)
PARAMETER
LOW-POWER MODES
MIN
TYP
MAX
UNIT
td(WAKE-A)
Delay time, CLKOUT switching to
program execution resume
IDLE1
LPM0
4 + 6 tc(CO)
15
ns
tc(CO)
td(IDLE-COH)
Delay time, Idle instruction exe-
cuted to CLKOUT high
IDLE2
LPM1
4tc(CO)
ns
td(WAKE-OSC)
Delay time, wakeup interrupt
asserted to oscillator running
HALT
{PLL/OSC power down}
LPM2
OSC start-up
and PLL lock
time
ms
td(IDLE-OSC)
Delay time, Idle instruction exe-
cuted to oscillator power off
4tc(CO)
μ
s
td(EX)
Delay time, reset vector executed
after RS high
36H
ns
Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
WAKE INT
WAKE INT can be any valid interrupt or RESET
CLKOUT
A0–A15
td(WAKE–A)
Figure 19. IDLE1 Entry and Exit Timing – LPM0
td(WAKE–A)
td(IDLE–COH)
WAKE INT
CLKOUT
A0–A15
WAKE INT can be any valid interrupt or RESET
Figure 20. IDLE2 Entry and Exit Timing – LPM1
td(EX)
td(IDLE–COH)
td(IDLE–OSC)
áá
áá
RESET
CLKOUT
A0–A15
td(WAKE–OSC)
Figure 21. HALT Mode – LPM2
A
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