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參數(shù)資料
| 型號： | TMS320C240PQL |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 94/105頁 |
| 文件大小： | 1481K |
| 代理商： | TMS320C240PQL |
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TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
94
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
VCCA= 5 5 V
VCCA = 5.5 V
converting
5
ICCA
Analog supply current
non-converting
2
mA
VCCA = VREFHI = 5.5 V
PLL or OSC power
down
1
Iref
Input charge current, VREFHI or VREFLO
VCCA = VCCD = VREFHI = 5.5 V, VREFLO = 0 V
Typical capacitive load on
analog input pin
5
mA
Ci
Cai
Analog input capacitance
non-sampling
6
pF
sampling
8
ZAI
Analog input source impedance
Analog input source impedance for conversions to
remain within specifications.
9
k
EDNL
Differential nonlinearity error
Difference between the actual step width and the ideal
value
– 1
1.5
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight line through
the ADC transfer characteristics, excluding the
quantization error
1.5
LSB
td(PU)
Absolute resolution = 4.89 mV. At VREFHI = 5 V and VREFLO = 0 V, this s one LSB. As VREFHI decreases, VREFLO ncreases, or both, he LSB sizes
decrease. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10
s
The ADC module allows complete freedom in the design of the sources for the analog inputs. The period of the
sample time is independent of the source impedance. The sample-and-hold period occurs in the first half-period
of the ADC clock after the ADCIMSTART bit or the ADCSOC bit of the ADC control register 1 (ADCTRL1, bits 13
and 0, respectively) is set to 1. The conversion then occurs during the next six ADC clock cycles. The digital
result registers are updated on the next ADC clock cycle once the conversion is completed.
ADC input pin circuit
One of the most common A/D application errors is inappropriate source impedance. In practice, minimum
source impedance should be used to limit the error as well as minimize the required sampling time; however,
the source impedance must be smaller than Z
AI
. A typical ADC input pin circuit is shown in Figure 47.
VIN
R1
Requiv
VAI
(to ADCINx input)
R1 = 9 k
typical
Figure 47. Typical ADC Input Pin Circuit
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PDF描述 |
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| TMS320C240PQQ | 16-Bit Microcontroller |
| TMS320F240PQL | 16-Bit Microcontroller |
| TMS320F240PQQ | 16-Bit Microcontroller |
| TMS320F240PQS | 16-Bit Microcontroller |
| TMS320LC31-40 | Digital Signal Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320C240PQQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMS320C241 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C241FNS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C241PGS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLER |
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