
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
89
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SPI SLAVE MODE TIMING PARAMETERS
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0)
(see Figure 45)
MIN
MAX
UNIT
tc(SPC)S
tw(SPCH)S§
tw(SPCL)S§
tw(SPCL)S§
tw(SPCH)S§
td(SPCH-SOMI)S§
td(SPCL-SOMI)S§
tv(SPCL-SOMI)S§
tv(SPCH-SOMI)S§
tsu(SIMO-SPCL)S§
tsu(SIMO-SPCH)S§
tv(SPCL-SIMO)S§
tv(SPCH-SIMO)S§
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
Cycle time, SPICLK
8tc
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S–70
0.5tc(SPC)S–70
0.5tc(SPC)S–70
0.5tc(SPC)S–70
0.375tc(SPC)S–70
0.375tc(SPC)S–70
0.75tc(SPC)S
0.75tc(SPC)S
0
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high (clock polarity = 0) to SPISOMI valid
ns
Delay time, SPICLK low (clock polarity = 1) to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK low (clock polarity =0)
ns
Valid time, SPISOMI data valid after SPICLK high (clock polarity =1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
ns
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
0.5tc(SPC)S
0.5tc(SPC)S
ns