![](http://datasheet.mmic.net.cn/260000/TMS320F240PQA_datasheet_15975211/TMS320F240PQA_87.png)
T
D
S
P
8
SPI master mode external timing parameters (clock phase = 1)
(see Figure 44)
WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
UNIT
MIN
MAX
MIN
MAX
tc(SPC)M
Cycle time, SPICLK
4tc
128tc
5tc
127tc
ns
tw(SPCH)M§
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M–70
0.5tc(SPC)M
0.5tc(SPC)M–0.5tc–70
0.5tc(SPC)M –0.5tc
ns
tw(SPCL)M§
tw(SPCL)M§
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M–70
0.5tc(SPC)M–70
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M–0.5tc–70
0.5tc(SPC)M+0.5tc–70
0.5tc(SPC)M –0.5tc
0.5tc(SPC)M + 0.5tc
Pulse duration, SPICLK low (clock polarity = 0)
tw(SPCH)M§
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M–70
0.5tc(SPC)M
0.5tc(SPC)M+0.5tc–70
0.5tc(SPC)M + 0.5tc
ns
tsu(SIMO-SPCH)M§
Setup time, SPISIMO data valid before SPICLK high
(clock polarity = 0)
0.5tc(SPC)M–70
0.5tc(SPC)M –70
ns
tsu(SIMO-SPCL)M§
Setup time, SPISIMO data valid before SPICLK low
(clock polarity = 1)
0.5tc(SPC)M–70
0.5tc(SPC)M –70
tv(SPCH-SIMO)M§
Valid time, SPISIMO data valid after SPICLK high
(clock polarity =0)
0.5tc(SPC)M–70
0.5tc(SPC)M –70
ns
tv(SPCL-SIMO)M§
Valid time, SPISIMO data valid after SPICLK low
(clock polarity =1)
0.5tc(SPC)M–70
0.5tc(SPC)M –70
tsu(SOMI-SPCH)M§
Setup time, SPISOMI before SPICLK high
(clock polarity = 0)
0
0
ns
tsu(SOMI-SPCL)M§
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
0
0
tv(SPCH-SOMI)M§
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
0.25tc(SPC)M–70
0.5tc(SPC)M–70
ns
tv(SPCL-SOMI)M§
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
0.25tc(SPC)M–70
0.5tc(SPC)M–70
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc = system clock cycle time = 1/SYSCLK = tc(SYS)
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).