參數(shù)資料
型號(hào)： TMS320C15-25
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號(hào)處理器（160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號(hào)處理器）
文件頁數(shù)： 68/139頁
文件大?。?/td> 1478K
代理商： TMS320C15-25
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
68
output disable
During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing
the output disable state. This state is selected by setting G and E pins high. While output disable is selected,
Q8-Q1are placed in the high-impedance state.
EPROM protection
To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code
from external accesses can be completely disabled. Programming the RBIT disables external access of the
EPROM cell and disables the microprocessor mode, making it impossible to access the code resident in the
EPROM cell. The only way to remove this protection is to erase the entire EPROM cell, thus removing the
proprietary information. The signal requirements for programming this bit are shown in Table 5. The cell can be
determined as protected by verifying the programming of the RBIT shown in the table.
standard programming procedure
Before programming, the device must first be completely erased. Then the device can be programmed with the
correct code. It is advisable to program unused sections with zeroes as a further security measure. After the
programming is complete, the code programmed into the cell should be verified. If the cell passes verification,
the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label
should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this
point, the programming is complete, and the device is ready to be placed into its destination circuit.
program cycle timing
A12-A0
Q8-Q1
VPP
VCC
E
PGM
G
Program
Verify
Address Stable
Address N+1
Data In Stable
Data Out
Valid
tsu(A)
th(A)
tsu(D)
tsu(VPP)
tdis(G)
tsu(VCC)
tsu(E)
th(D)
tw(IPGM)
tw(FPGM)
tsu(G)
ten(G)
VIH
VIL
VIH/VOH
VIL/VOL
VPP
VCC
VCC+1
VCC
VIH
VIL
VIH
VIL
VIH
VIL
HI-Z
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