參數(shù)資料
型號： TMS320C15-25
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 50/139頁
文件大小： 1478K
代理商： TMS320C15-25
tw(PGM)
Initial program pulse duration
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
50
erasure
Before programming, the
′
E14 must be erased by exposing it to ultraviolet light. The recommended minimum
exposure dose (UV-intensity
×
exposure-time) is 15 W
s/cm
2
. A typical 12-mW
s/cm
2
, filterless UV lamp will
erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After
exposure, all bits are in the high state.
verify/read
To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown
in Table 5, assuming the inhibit bit (RBIT) has not been programmed.
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.
standard programming procedure
Before programming, the
′
E14 must first be completely erased. The device can then be programmed with the
correct code. It is advisable to program unused sections with zeros as a further security measure. After the
programming is complete, the code programmed into the cell should be verified. If the cell passes verification,
the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label
should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this
point, the programming is complete, and the device is ready to be placed into its destination circuit.
Refer to other appendices of the TMS320C1x User’s Guidefor additional information on EPROM programming.
recommended timing requirements for programming: V
CC
= 6 V and V
PP
= 12.5 V (FAST) or
V
CC
= 6.5 V and V
PP
= 13 V (SNAP! PULSE), T
A
= 25
°
C (see Note 13)
MIN
NOM
MAX
UNIT
Fast programming algorithm
0.95
1
1.05
ms
μ
s
ms
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
SNAP! Pulse programming algorithm
95
100
105
tw(FPGM)
tsu(A)
tsu(E)
tsu(G)
tsu(D)
tsu(VPP)
tsu(VCC)
th(A)
th(D)
NOTE 13: For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V
±
0.5 V during
programming.
Final pulse duration
Fast programming only
2.85
78.75
Address setup time
2
E setup time
2
G setup time
2
Data setup time
2
VPP setup time
VCC setup time
Address hold time
2
2
0
Data hold time
2
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
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