參數(shù)資料
型號： TMS320C15-25
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 49/139頁
文件大?。?/td> 1478K
代理商： TMS320C15-25
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
49
NAME
I/O
DEFINITION
A12(MSB)-A0(LSB)
CLKIN
E
EPT
G
GND
PGM
Q8(MSB)-Q1(LSB)
RS
VCC
VPP
I
I
I
I
I
I
I
I/O
I
I
I
On-chip EPROM programming address lines
Clock oscillator input
EPROM chip enable
EPROM test mode select
EPROM output enable
Ground
EPROM write/program select
Data lines for byte-wide programming of on-chip 8K bytes of EPROM
Reset for initializing the device
5-V to 6.5-V power supply
12.5-V to 13-V power supply
Table 4 shows the programming levels required for programming, verifying, reading, and protecting the EPROM
cell.
Table 4. TMS320E14/P14 Programming Mode Levels
SIGNAL
NAME
TMS320E14/P14
PIN
TMS27C64
PIN
PROGRAM
PROGRAM
VERIFY
READ
EPROM
PROTECT
PROTECT
VERIFY
E
19
20
VIL
VIH
PULSE
VIL
VIL
VIH
VIH
VIH
VPP
VCCP
VSS
VSS
VPP
VIL
VIL
VIH
VCCP
VCCP
VSS
VSS
VPP
G
23
22
PULSE
PULSE
PGM
16
27
VIH
VPP
VCCP
VSS
VSS
VSS
VIH
VCC
VCC
VSS
VSS
VSS
VPP
VCC
VSS
CLKIN
18
1
VPP
VCCP
VSS
VSS
VSS
4,33
28
3,34
14
24
14
EPT
17
26
Q1-Q8
42, 41, 38, 37,
32-29
11–13, 15-19,
Data In
Data Out
Data Out
Q8 = PULSE
Q8 = RBIT
A12-A7
15, 11, 10, 8, 7, 2
2, 23, 21, 24,
25, 3
ADDR
ADDR
ADDR
X
X
A6
1
4
ADDR
ADDR
ADDR
X
VIL
X
A5
68
5
ADDR
ADDR
ADDR
X
A4
67
6
ADDR
ADDR
ADDR
VIH
X
X
A3-A0
66, 65, 56, 55
7-10
ADDR
ADDR
ADDR
X
Signal names shown for
′
E14/P14 EPROM programming mode only.
Legend:
VIH
= TTL high level; VIL = TTL low level; ADDR = byte address bit; VPP = 12.5 V
±
0.25 V (FAST) or 13 V
±
0.25 V (SNAP! Pulse).
VCC
=
5 V
±
0.25 V; X = don’t care; PULSE = low-going TTL pulse.
DIN
= byte to be programmed at ADDR; QOUT = byte stored at ADDR.; RBIT = ROM protect bit
VCCP= 6 V
±
0.25 V (FAST) or 6.5 V
±
0.25 V (SNAP! Pulse).
programming
Since every memory in the cell is at a logic high, the programming operation reprograms selected bits to low.
Once the
′
320E14 is programmed, these bits can only be erased using ultraviolet light. The correct byte is placed
on the data bus with V
PP
set to the 12.5-V level. The PGM pin is then pulsed low to program in the zeros.
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