參數(shù)資料
型號: TMS320C10-14
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(280ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的DSP)
中文描述: 數(shù)字信號處理器(280ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的數(shù)字信號處理器)
文件頁數(shù): 73/139頁
文件大小: 1478K
代理商: TMS320C10-14
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
73
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
10
1/4 tc(C)–5
–10
1/4 tc(C)–5
–10
1/2 tc(C)–5
–10
MAX
UNIT
td1
td2
td3
td4
td5
td6
td7
td8
td9
td10
tv
th(A-WMD)
tsu(A-MD)
Values derived from characterization data and not tested.
NOTE 14: Address bus will be valid upon WE
, MEN
, or DEN
.
Delay time CLKOUT
to address bus valid
75
ns
Delay time CLKOUT
to MEN
1/4 tc(C)+25
ns
Delay time CLKOUT
to MEN
30
ns
Delay time CLKOUT
to DEN
1/4 tc(C)+25
ns
Delay time CLKOUT
to DEN
30
ns
Delay time CLKOUT
to WE
1/2 tc(C)+25
ns
Delay time CLKOUT
to WE
30
ns
Delay time CLKOUT
to data bus OUT valid
1/4 tc(C)+75
ns
Time after CLKOUT
that data bus starts to be driven
1/4 tc(C)–5
ns
Time after CLKOUT
that data bus stops being driven
1/4 tc(C)+60
ns
Data bus OUT valid after CLKOUT
1/4 tc(C)–10
0
– 4
ns
Address hold time after WE
,
MEN
, or
DEN
(see Note 14)
ns
Address bus setup time to DEN
ns
timing requirements over recommended operating conditions
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tsu(D)
Setup time data bus valid prior to CLKOUT
56
ns
th(D)
Hold time, data bus held valid after CLKOUT
(see Note 9)
0
ns
NOTE 9:
Data may be removed from the data bus upon MEN
or DEN
preceding CLKOUT
.
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