參數(shù)資料
型號： TMS320C10-14
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 30/139頁
文件大?。?/td> 1478K
代理商： TMS320C10-14
I/O/Z
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
30
Each device can execute programs form either internal (MC/MP=0) or external program memory (MC/MP=1).
For proprietary code security, the
′
E14 and
′
P14 incorporate an EPROM protect bit (RBIT). If this bit is
programmed, the device’s internal program memory cannot be accessed by any external means.
TERMINAL FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
ADDRESS/DATA BUSES
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2/PA2
A1/PA1
A0/PA0
5
6
9
12
13
14
20
21
25
26
27
28
O/Z
Program memory address bus A11 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through
PA0 (LSB). Addresses A11 through A0 are always active and never go to high impedance except
during reset. During execution of the IN and OUT instructions, pins 26, 27, and 28 carry the port
addresses. Pins A3 through A11 are held high when port accesses are made on pins PA0 through
PA2.
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
35
36
39
40
43
46
49
50
57
58
59
60
61
62
63
64
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state
except when WE is active (low). The data bus is also active when internal peripherals are written to.
INTERRUPT AND MISCELLANEOUS SIGNALS
INT
18
I
External interrupt input. The interrupt signal is generated by a high-to-low transition on this pin.
NMI/MC/MP
22
I
Non-maskable interrupt. When this pin is brought low, the device is interrupted irrespective of the
state of the INTM bit in status register ST.
Microcomputer/microprocessor select. This pin is also sampled when RS is low. If high during reset,
internal program memory is selected. If low during reset, external memory will be selected.
WE
15
O
Write enable. When active low, WE indicates that device will output data on the bus.
REN
16
O
Read enable. When active low, REN indicates that device will accept data from the bus.
RS
17
I
Reset. When this pin is low, the device is reset and PC is set to zero.
Continued next page.
Input/Output/High-impedance state.
相關(guān)PDF資料
PDF描述
TMS320C10-25 Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TMS320C10-25 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS
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TMS320C10FNA 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS
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